Semiconductor memory and information processing system

Details Semiconductor memory and information processing system Semiconductor memory and information processing system

2011-05-10

2011-05-10

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711SE12091

Reexamination Certificate

active

07941589

ABSTRACT:
A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221. . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.

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patent: 2007/0101193 (2007-05-01), Johnson et al.
patent: 2008/0201536 (2008-08-01), Hars
patent: 2009/0070885 (2009-03-01), Mersh
patent: 2005-108273 (2005-04-01), None

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