Semiconductor memory and burn-in test method of...

Details Semiconductor memory and burn-in test method of... Semiconductor memory and burn-in test method of...

2007-04-03

2007-04-03

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S069000, C365S203000

Reexamination Certificate

active

11260486

ABSTRACT:
A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

REFERENCES:
patent: 5995427 (1999-11-01), Tsukikawa
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 7023748 (2006-04-01), Matsumoto
patent: 10-340598 (1998-12-01), None
patent: 2000-149588 (2000-05-01), None
patent: 2004-355720 (2004-12-01), None
patent: 2000-0035149 (2000-06-01), None

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