Semiconductor memory

Details Semiconductor memory Semiconductor memory

1998-10-29

1999-11-09

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700

Patent

active

059826800

ABSTRACT:
A memory cell array is composed of N (1.ltoreq.N.ltoreq.Nmax) blocks. A redundancy memory is always composed of Nmax blocks. A block decoder selects one of the N blocks of the memory cell array based on a block address signal. A redundancy memory decoder selects one of the Nmax blocks of the redundancy memory based on a redundancy memory selection address signal. When the number of blocks of the memory cell array and the number of blocks of the redundancy memory are different from each other, the N blocks of the memory cell array are in a one to one correspondence with N blocks of the Nmax blocks of the redundancy memory and the redundancy memory decoder selects one of the N blocks of the redundancy memory. The other blocks than the N blocks of the redundancy memory are left unused.

REFERENCES:
patent: 5475648 (1995-12-01), Fujiwara
Fujii, et al. "A Low-Power Sub 100 ns 256K Bit Dynamic RAM," IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 441-445.

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