Semiconductor memory

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365 63, 365208, 365230, G11C 1300

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active

045861714

ABSTRACT:
A random access type semiconductor memory comprises a plurality of word lines (44; 54) of a metal arranged in parallel, at least first to fourth bit lines (BL1, BL2, BL1, BL2) orthogonal to the word lines, a plurality of memory cells (48; 58a, 58b), each of which is arranged corresponding to one of cross points between each of the word lines and each of the bit lines, a first sense amplifier (SA1) connected to the first and third bit lines (BL1, BL1) and a second sense amplifier (SA2) connected to the second and fourth bit lines (BL2, BL2). The first sense amplifier (SA1) amplifies a voltage applied to said first or third bit line from a selected first memory cell and the second sense amplifier (SA2) amplifies a voltage applied to the second or fourth bit line from a selected second memory cell.

REFERENCES:
patent: 3209337 (1965-09-01), Crawford
patent: 3678473 (1972-07-01), Wahlstrom
patent: 3771148 (1973-11-01), Aneshausley
patent: 4025907 (1977-05-01), Karp et al.
patent: 4160275 (1979-07-01), Lee et al.
patent: 4287576 (1981-09-01), Pricer
"A 1-.mu.m Mo-Poly 64-kbit MOS RAM", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 667-671.
"One-Device Cells for Dynamic Random-Access Memories: A Tutorial"; IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, Jun. 1979, pp. 839-852.

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