Semiconductor memory

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

365174, 365192, G11C 1100

Patent

active

054693802

ABSTRACT:
A semiconductor memory having NMOS write transistors (16, 14) formed in series between a node (N1) of a memory cell (MC) and a ground level, the gate of the transistor (16) being connected to a write word line (4), the gate of the transistor (14) being connected to a first column write line (12), and NMOS write transistors (17, 15) are formed in series between a node (N2) of the memory cell (MC) and the ground level, the gate of the transistor (17) being connected to the write word line (4), the gate of the transistor (15) being connected to a second column write line (13), to thereby achieve a normal write operation when the power supply voltage is low, with power consumption reduced.

REFERENCES:
patent: 3660827 (1972-05-01), Tickle
patent: 5245575 (1993-09-01), Sasaki et al.

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