Semiconductor memory

Static information storage and retrieval – Read/write circuit – Noise suppression

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Details

307542, 365226, G11C 702

Patent

active

044208235

ABSTRACT:
A static semiconductor memory having a plurality of memory cells respectively connected to word lines and connected in parallel to bit line pairs and having a power-down function, is provided with a coupling noise canceller connected to a data bus which is connected at one end to a bit line via a transfer gate and at the other end to a sense amplifier. When the static semiconductor memory is placed in a power-down mode, the coupling noise canceller operates to clamp the data bus at a predetermined potential; thus preventing an increase in the access time when the chip is accessed from the power-down state rather than the active state.

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patent: 4223394 (1980-09-01), Patlak et al.
patent: 4336465 (1982-06-01), Nakano et al.

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