Semiconductor memory

Details Semiconductor memory Semiconductor memory

1998-10-22

2000-08-01

Elms, Richard

Static information storage and retrieval

Read/write circuit

Differential sensing

365 51, 365 63, G11C 702

Patent

active

060976543

ABSTRACT:
A semiconductor memory of wherein the delay of control signals for controlling sense amplifiers is efficiently controlled, without extensively changing a currently-used fabricating process. A dummy bit line pair are arranged between desired bit line pairs in the memory cell array. Since the dummy bit line pair is not related to a normal operation such as reading data stored in memory cells, it is not necessary to dispose a sense amplifier in an area of a sense amplifier array adjacent to the dummy bit line pair. As a result, there is formed a free area in the sense amplifier array. The free area has at least a width between the dummy bit line pair. This free area further forms a contact portion for electrically connecting sense amplifier control signal lines and low resistance sense amplifier control signal lines. That is, this free area is utilized as a shunt area of the sense amplifier control signal lines.

REFERENCES:
patent: 5255231 (1993-10-01), Oh
patent: 5359216 (1994-10-01), Coleman et al.
patent: 5483495 (1996-01-01), Fukuda
patent: 5886939 (1999-03-01), Choi et al.

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