Semiconductor memory

Details Semiconductor memory Semiconductor memory

1997-10-29

1999-09-21

Nelms, David

Static information storage and retrieval

Addressing

Multiple port access

36518905, 36523008, G11C 800

Patent

active

059562870

ABSTRACT:
The present invention provides a semiconductor memory capable of improving a write address generator which performs complained control by using many gates and capable of reducing layout area. A FIFO semiconductor memory having plural input ports is provided with a memory array MARRAY of m-word.times.n bit.times.2-having 1W1R cell, a write address generator WAG consisted of a shift register, a valid bit VB of m-word.times.2-bit having 1W1R cell, a write buffer WDBV for the valid bit, a valid bit sense amplifier SAV, a read control RCTL judging validness of read data and a read address generator having a circuit controlling update of read address.

REFERENCES:
patent: 4794566 (1988-12-01), Richards et al.
patent: 5255238 (1993-10-01), Ichige et al.
patent: 5339268 (1994-08-01), Machida
patent: 5404332 (1995-04-01), Sato et al.

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