Semiconductor memory

Details Semiconductor memory Semiconductor memory

2006-12-13

2009-02-24

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S185050, C365S185070, C365S189040, C365S230050

Reexamination Certificate

active

07495948

ABSTRACT:
In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

REFERENCES:
patent: 7345919 (2008-03-01), Honda et al.
patent: 7391667 (2008-06-01), Atwood et al.
patent: 2004/0141362 (2004-07-01), Sumitani et al.
patent: 2005/0013160 (2005-01-01), Higeta et al.
patent: 55-64686 (1980-05-01), None
Y. Kagenishi et al. “Low Power Self Refresh Mode DRAM With Temperature Detecting Circuits”, Memory Division, Matsushita Electronics, Corp. p. 43-44. Japan.
K. Nii et al. “A 90nm Dual-Port SRAM with 2.04μ m28T-Thin Cell Using Dynamically-Controlled Column Bias Scheme” IEEE International Solid-State Circuits Conference Digest of Technical Papers, p. 508-510, 2004.

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