Semiconductor memory

Details Semiconductor memory Semiconductor memory

2007-08-07

2007-08-07

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S191000, C365S194000, C365S203000, C365S205000

Reexamination Certificate

active

11338670

ABSTRACT:
In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input into a write control circuit, to delay start of the write operation until termination of the read operation. This can delay the timing of activating a write word line by a write row decoder behind the timing of activating a read word line by a read row decoder, to allow the read operation first followed by the write operation. Therefore, since the read operation is performed while the write word line being kept closed, the trouble of data processing becoming uncertain due to addition of the load of a write bit line to a read bit line can be prevented.

REFERENCES:
patent: 5335199 (1994-08-01), Aoyama
patent: 6473357 (2002-10-01), Fan et al.
patent: 6785157 (2004-08-01), Arimoto et al.
patent: 6958507 (2005-10-01), Atwood et al.
patent: 07-175713 (1995-07-01), None

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