Semiconductor memory

Details Semiconductor memory Semiconductor memory

2007-11-13

2007-11-13

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S189040

Reexamination Certificate

active

11513394

ABSTRACT:
A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

REFERENCES:
patent: 6219292 (2001-04-01), Jang
patent: 6349068 (2002-02-01), Takemae et al.
patent: 6560155 (2003-05-01), Hush
patent: 6744685 (2004-06-01), Mizugaki
patent: 6829192 (2004-12-01), Shinozaki et al.
patent: 2002/0191466 (2002-12-01), Hwang et al.
patent: 2003/0218931 (2003-11-01), Okamoto et al.

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