Semiconductor memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S065000, C365S207000

Reexamination Certificate

active

11134332

ABSTRACT:
A ferroelectric memory has a plurality of memory cells respectively having a cell transistor and ferroelectric capacitor whose one terminal is connected with the cell transistor, a plurality of word lines respectively connected with said cell transistor, a plurality of plate lines connected with the other terminal of said ferroelectric capacitor and intersecting with said word lines, a plurality of local bit lines connected with said cell transistors, and a global bit line that is selectively connected with local bit lines. Furthermore, the ferroelectric memory has a sensing amplifier unit that detects the amount of charging of the local bit lines from said memory cells while maintaining the potential of the local bit lines at a potential equivalent to the non-selected plate lines, during reading.

REFERENCES:
patent: 2004/0042286 (2004-03-01), Kato et al.
patent: 2004/0047172 (2004-03-01), Komatsuzaki
patent: 2005/0254282 (2005-11-01), Summerfelt et al.
patent: 2000-195278 (2000-07-01), None
patent: 2002-133857 (2002-05-01), None
patent: 2003-197869 (2003-07-01), None
patent: 2000-43969 (2000-07-01), None
Shoichiro Kawashima, et al, “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”, IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 592-598.

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