Semiconductor memory

Details Semiconductor memory Semiconductor memory

2007-03-06

2007-03-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S201000, C365S222000, C365S240000

Reexamination Certificate

active

11291777

ABSTRACT:
A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lines upon every refresh request. An activation circuit activates any of the normal word lines and redundancy word line according to an output of the shift register. A first storing circuit stores in advance a defect address indicating a defective normal memory cell row. A first activation control circuit prohibits activation of a normal word line corresponding to the defect address stored in the first storing circuit when the output of the shift register indicates the normal word line.

REFERENCES:
patent: 4989181 (1991-01-01), Harada
patent: 5200707 (1993-04-01), Weaver
patent: 5479370 (1995-12-01), Furuyama et al.
patent: 5968190 (1999-10-01), Knaack
patent: 2002/0001246 (2002-01-01), Hidaka
patent: 2003/0043672 (2003-03-01), Inoue et al.
patent: 11-120790 (1999-04-01), None
patent: 2000-311487 (2000-11-01), None
patent: 2002-8370 (2002-01-01), None
patent: 2003-68071 (2003-03-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3741417