Semiconductor memory

Details Semiconductor memory Semiconductor memory

2005-12-20

2005-12-20

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S718000

Reexamination Certificate

active

06978402

ABSTRACT:
A synchronous semiconductor memory operating in synchronization with an external clock signal has (a) a mode selector to select one of a normal mode and a test mode, (b) a clock generator to generate, in the test mode, an internal clock signal whose frequency is higher than the frequency of the external clock signal, (c) an address generator to generate, in the test mode, internal addresses in synchronization with the internal clock signal, the internal clock signal and internal addresses being used in the test mode to carry out a test and provide test result data, and (d) an output data controller to select, in the test mode, part of the test result data and provide the selected part as output data in synchronization with the external clock signal.

REFERENCES:
patent: 5875153 (1999-02-01), Hii et al.
patent: 5910181 (1999-06-01), Hatakenaka et al.
patent: 6058056 (2000-05-01), Beffa et al.
patent: 6069829 (2000-05-01), Komai et al.
patent: 6467053 (2002-10-01), Connolly et al.
patent: 6493647 (2002-12-01), Chiang et al.
patent: 6526533 (2003-02-01), Cowles et al.
patent: 2003/0070121 (2003-04-01), Mori et al.

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