Semiconductor memory

Details Semiconductor memory Semiconductor memory

2005-08-30

2005-08-30

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S051000, C365S063000

Reexamination Certificate

active

06937532

ABSTRACT:
A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

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Hiroshi Shimizu et al., (1999), “A 1.4ns Access 700MHz 288kb SRAM Macro with Expandable architecture” in 1999 IEEE International Solid-State Circuits Conference, Session 11, Paper TA 11.1, pp. 190-191.

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