Semiconductor memory

Details Semiconductor memory Semiconductor memory

2003-01-03

2004-12-07

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S189040

Reexamination Certificate

active

06829192

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory which requires fresh operations to retain data written in its memory cells.
2. Description of the Related Art
Hand-held terminals such as cellular phones are growing in memory capacity requirement year by year. Under the circumstances, dynamic RAMs (hereinafter, referred to as DRAMs) have come to be used as the work memories of the cellular phones instead of conventional static RAMs (hereinafter, referred to as SRAMs). DRAMs are smaller than SRAMs in the numbers of devices that constitute the memory cells. DRAMs can thus be reduced in chip size, with lower chip cost than that of SRAMs.
Meanwhile, semiconductor memories to be mounted on cellular phones must be low in power consumption so as to allow prolonged use of the batteries. Unlike SRAMs, DRAMs require periodic refresh operations in order to retain data written in their memory cells. Consequently, when DRAMs are used as the work memories of cellular phones, data retention alone can consume power to exhaust the batteries even if the cellular phones are not in use.
In order to reduce the power consumption of the DRAMs during standby (in low power consumption mode), there have been developed partial refresh technology and twin cell technology.
According to the partial refresh technology; the number of memory cells to be refreshed is reduced by limiting the number of memory cells to retain data in a standby state. Reducing the memory cells to refresh can decrease the number of times of refresh, with a reduction in the power consumption during standby.
According to the twin cell technology, complementary data is stored into two memory cells (memory cell pair) which are connected to complementary bit lines, respectively. This doubles the charges retained in the memory cell pair. Since the two memory cells retain “H” data and “L” data, respectively, the refresh interval is determined by a longer one between the data retention times of “H” data and “L” data. That is, the worst data retention time is the sum of the characteristics of the two memory cells, not the characteristic of one single memory cell. On the contrary, in a single memory cell, the refresh interval is determined by a shorter one between the data retention times of “H” data and “L” data. As above, according to the twin cell technology, retaining data in two memory cells makes it possible to compensate a small leak path, if any, in one of the memory cells with the other memory cell.
In the partial refresh technology described above, to reduce the power consumption during the low power consumption mode requires that the data retention areas be small. As a result, the lower the power consumption, the smaller the memory capacity available for retention during the low power consumption mode.
In the twin cell technology, two memory cells are always used to retain a single bit of data not only in refresh operations but also in normal read operations and write operations. Storing a single bit hence requires a memory cell size twice as big as that of a single memory cell, which results in increasing chip cost. Consequently, in the cases of DRAMs to which the twin cell technology is applied, there is not much advantage in replacing the SRAMs mounted on cellular phones with the DRAMs.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the power consumption of a semiconductor memory in low power consumption mode, the semiconductor memory having memory cells that require refresh operations.
According to one of the aspects of the semiconductor memory of the present invention, a partial area for retaining data in low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption in the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, a word line control circuit of the operation control circuit enables selection of a partial word line of word lines connected to the memory cells and disables selection of the other word lines, the partial word line being connected to the memory cell in the partial area. A sense amplifier control circuit of the operation control circuit keeps activating the sense amplifier during the low power consumption mode. Since the selection of the word lines other than in the partial area is disabled during the low power consumption mode, the sense amplifier keeps latching the data that is read from the memory cell. Consequently, data crash can be avoided during the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, the word line control circuit keeps selecting the partial word line during the low power consumption mode while the sense amplifier keeps latching the data. This simplifies the selecting/deselecting control of the word lines. That is, it is possible to reduce the scale of the control circuit for the word lines.
According to another aspect of the semiconductor memory of the present invention, a booster for supplying a boost voltage to the word lines stops its operation after the sense amplifier latches data at the start of the low power consumption mode. In returning from the low power consumption mode to the normal operation mode, the booster starts a boost operation again. Since the booster is operated only when the selecting operation of the word lines is necessary, the power consumption in the low power consumption mode can be reduced further.
According to another aspect of the semiconductor memory of the present invention, a mask circuit disables the selection of the word lines in response to a refresh control signal in the low power consumption mode. The semiconductor memory is thus prevented from malfunctioning.
According to another aspect of the semiconductor memory of the present invention, its operation mode shifts to the normal operation mode or the low power consumption mode in accordance with a chip enable signal for operating the semiconductor memory. Thus, shifting of the operation mode of the semiconductor memory can be made by simple control. This enables a simple configuration of the control circuit of a system implementing the semiconductor memory.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit selects first and second word lines simultaneously in second and subsequent refresh operations on each of the partial areas in the low power consumption mode. The operation control circuit can thus be configured simply.
According to another aspect of the semiconductor memory of the present invention, a plurality of partial areas for retaining data during low power consumption mode are each composed of a predetermined number of memory cells, of memory cells connected to a bit line. A refresh control circuit cyclically outputs a refresh control signal for refreshing the memory cells. An operation control circuit performs a read operation, a write operation, and a refresh operation on the memory cells. The partial areas each include a single first memory cell and at least a single second memory cell which are of the memory cells connected to the bit line.
At the start of the low power consumption mode, the operation control circuit performs a refresh operation on data retained in the first memory cell. The data is amplified by a sense amplifier and written to the first and second memory

Affiliated with

Also associated with

Rating

Semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3327807