Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-03-29

2004-11-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S185230

Reexamination Certificate

active

06819592

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory employing electrically rewritable memory cells. More specifically, the present invention relates to a semiconductor memory which constitutes memory cell units by connecting memory cells in series.
2. Related Background Art
Normally, an EEPROM memory cell has a MISFET structure in which a charge accumulation layer and a control gate are layered. This memory cell stores data in a nonvolatile manner based on the difference between a threshold voltage at the state of injecting electric charge into the charge accumulation layer and a threshold voltage at the state of discharging the electric charge. The injection and emission of charges are carried out by a tunnel current through a tunnel insulating film provided between the charge accumulation layer and a substrate channel.
Among EEPROM's, a so-called NAND type EEPROM which constitutes NAND cell units by connecting a plurality of memory cells in series requires fewer selected transistors than an NOR type EEPROM, thereby realizing higher integration.
In order to read data from the NAND type EEPROM, a read voltage for threshold voltage determination is applied to the control gate of a selected memory cell in the NAND cells, a pass voltage higher than the read voltage for turning on the memory cell irrespective of data is applied to the control gates of the remaining unselected memory cells and a current penetrating the NAND cell string is detected. Therefore, even if the same data is written, the read current differs according to the state of data of the unselected memory cells and the position of the selected memory cell in the NAND cells. Further, since data is read according to the quantity of charges which pass the current terminals of the memory cells, the apparent threshold voltage of each memory cell disadvantageously changes.
The generation of the difference in read current according to the data states of the unselected memory cell and the position of the selected memory cell will be specifically described with reference to
FIGS. 41
to
43
.
FIGS. 41 and 42
show different read conditions for a NAND cell unit constituted by connecting 16 memory cells M
0
to M
15
in series, respectively. One end of a NAND cell is connected to a data transfer line (bit line) BL through a select transistor S
1
and the other end thereof is connected to a common source line SL having a reference potential through a select transistor S
2
. The control gate of the respective memory cells M
0
to M
15
are connected to different data control lines (word lines) WL
0
to WL
15
, respectively and the gates of the select transistors S
1
and S
2
are connected to select gate lines SSL and GSL for block selection, respectively.
While each of
FIGS. 41 and 42
shows only one NAND cell unit, a plurality of NAND cell units of this type are arranged in a bit line direction and a word line direction and a memory cell array is thereby formed. In addition, a sense amplifier/data register is connected to the bit line BL. In a flash memory, the range of a plurality of NAND cell units aligned in the word line direction serves as a block which is a unit of batch erasure of data. Description will be given hereinafter while assuming that a state, in which electrons are discharged from the charge accumulation layer and a threshold voltage is low, is a “1” data state (erasure state) and a state, in which electrons are injected into the charge accumulation layer and a threshold voltage is high, is a “0” data state.
FIGS. 41A and 41B
show the read voltages when the memory cell M
0
closest to the bit line BL among the memory cells M
0
to M
15
is selected. In this case, the common source line SL has a ground potential GND, the bit line BL is applied with, for example, a positive voltage VBL of about 1V, the selected word line WL
0
is applied with a read voltage Vr for threshold voltage determination and the remaining unselected word lines WL
1
to WL
16
are each applied with a pass voltage Vread necessary to turn on a cell irrespective of the data. In addition, each of the select gate lines SSL and GSL is applied with the pass voltage Vread, as well.
FIG. 43
shows an example of the threshold voltage distribution of a memory cell which stores binary data. The upper limit Vthw of the threshold voltage of the “0” data is set at 2V, the upper limit Vthe of the threshold voltage of the “1” data (erasure state) is set at −1V and the pass voltage Vread is set at a voltage between 4 to 5V, for example. In addition, the read voltage Vr is set at, for example, 0V. While
FIG. 43
shows the threshold voltages of the select transistors S
1
and S
2
, they are lower than the upper limit Vthw of the write threshold voltage of a memory cell. By applying the pass voltage Vread to the select transistors S
1
and S
2
have, therefore, the select transistors S
1
and S
2
have higher conductance than that of each memory cell or are sufficiently kept conductive.
FIG. 41A
shows that the selected memory cell M
0
has “1” data and each of the remaining unselected memory cells M
1
to M
15
has “1” data, as well.
FIG. 41B
shows that the selected memory cell M
0
has “1” data and each of the remaining unselected memory cells M
1
to M
15
has “0” data. In these two cases, the relationship between read currents ID
1
and ID
2
which are carried to the NAND cell unit satisfies ID
1
>ID
2
. This is because the case shown in
FIG. 41B
is higher than that shown in
FIG. 41A
in the resistance between the source and the drain of each of the unselected memory cells M
1
to M
15
.
FIGS. 42A and 42B
show the relationship among read voltages in the case where the memory cell M
15
closest to the common source line SL of the NAND cells is selected.
FIG. 42A
shows that each of the memory cells M
0
to M
15
has “1” data and
FIG. 42B
shows that the selected memory cell M
15
has “1” data and each of the remaining unselected memory cells M
0
to M
14
has “0” data. In these cases, if the voltage VBL is lower than (Vread−Vthw), each of the memory cells M
0
to M
14
operates in a linear region. The case shown in
FIG. 42B
is higher in series resistance than the case shown in FIG.
42
A. In addition, the memory cell M
15
also operates in the linear region and the voltage between the drain and the source of the memory cell M
15
is low. Further, the relationship between read currents ID
3
and ID
4
shown in
FIGS. 42A and 42B
, respectively, satisfies ID
3
>ID
4
.
If the substrate bias effect of each memory cell is taken into account, the memory cell M
0
closer to the data transfer line BL is applied with a higher substrate bias than that of the memory cell M
15
closer to the common source line SL. As a result, ID
2
becomes lower than ID
4
and ID
1
becomes lower than ID
3
.
A problem in which the threshold voltage at the erasure state rises occurs by carrying out the erasure, write and read sequences, as shown in
FIGS. 44A and 44B
, even if the same data is written. Hereinafter, such a problem will be described.
In
FIG. 44A
, the memory cells M
0
to M
15
in the NAND cell unit are batch-erased and each is set in a “1” data state (in a step SE
1
). In a step SE
2
, the data of the memory cell M
0
is read in the voltage relationship shown in FIG.
41
A and it is determined whether the data is “0” or “1” at a constant current level Ith. Alternatively, the data may be determined not by applying the constant current Ith but by, for example, precharging the data transfer line with VBL to turn the data transfer line into a floating state, reading the data and detecting the potential change of the data transfer line using a sense amplifier. Further, “0” data is written to each of the memory cells M
1
to M
15
and the threshold voltage thereof is raised (in a step SE
3
). Next, in a step SE
4
, the data of the memory cell M
0
is read in the voltage relationship shown in FIG.
41
B and it is determined whether the data thus read is “0” or “1” at the constan

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