Semiconductor memory

Details Semiconductor memory Semiconductor memory

2003-07-29

2004-12-14

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06831870

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-251851, filed on Aug. 29, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having a redundancy circuit for relieving a defect occurring in a fabrication process.
2. Description of the Related Art
For the sake of improving a conforming rate, or yield, and reducing chip cost, semiconductor memories such as a DRAM have a redundancy circuit for relieving a defect occurring in a fabrication process. In a testing process, a circuit containing a defect is replaced with the redundancy circuit to relieve the defect.
In the meantime, during the development of semiconductor memories or immediately after the start of mass production thereof, defect analysis is important in improving the yield. Feeding back the result of the defect analysis to the fabrication process can stabilize the yield at an early stage.
In the defect analysis mentioned above, an electric analysis using an LSI tester is initially conducted to identify defective points. Here, when the LSI tester judges memory cells defective, the positions thereof are output as a fail bit map. The fail bit map is extremely useful since the test result from the LSI tester can be seen visually. Then, actual defective points (specific memory cells, sense amplifiers, word lines, decoders, or the like) are identified based on the fail bit map. Subsequently, the defective points are subjected to a physical analysis under a microscope or the like, so that the causes of the defects are identified.
In conventional semiconductor memories having a redundancy circuit, however, correspondence between the bit lines and the numbers of the data terminals might sometimes vary depending on whether or not the circuit containing a defect is replaced with the redundancy circuit. Specifically, there has been a problem that a bit line corresponding to a bit-
0
data terminal before the replacement with the redundancy circuit may be associated with a bit-
1
data terminal after the replacement with the redundancy circuit.
On this account, it takes a great deal of time to identify defective points during the physical analysis in particular. Consuming a great amount of time for the defect analysis results in delaying the feedback to the fabrication process, which makes the yield stabilization at an early stage difficult.
To solve this problem for smooth physical analysis, two fail bit maps are conventionally created depending on whether or not the redundancy circuit is used. With two fail bit maps, however, the testing and designing time increases and reduces the design efficiency. Besides, using the two fail bit maps for intended purpose is inconvenient.
SUMMARY OF THE INVENTION
It is an object of the present invention to establish uniform correspondence between the bit lines and the numbers of the data terminals regardless of whether or not the redundancy circuit is used, thereby reducing the time necessary for defect analysis.
According to one of the aspects of the semiconductor memory of the present invention, sub memory units each have a plurality of bit lines connected to memory cells, respectively, a plurality of sense amplifiers connected to the bit lines, respectively, and a plurality of column switch circuits for connecting the bit lines to data bus lines, respectively. The bit lines in each sub memory unit correspond to different data terminals. The sub memory units are arranged in a direction orthogonal to a wiring direction of the bit lines.
Main memory units are each composed of an even number of sub memory units having different addresses from each other. A redundancy memory unit has the same configuration as that of the main memory unit. The redundancy memory unit is enabled when a defective sub memory unit out of the sub memory units in the main memory units is disabled. That is, when the semiconductor memory has defects, defect relief is exercised on a sub memory unit basis. In each of the main memory units, column switch areas in which the column switch circuits are arranged are formed in mirror symmetry in the wiring direction of the bit lines.
Arranging the column switch areas in mirror symmetry allows the sequence of the data terminal numbers of the bit lines in the case of relieving a defect, in which the redundancy memory unit is used, to be easily made the same as in the case of not relieving a defect, in which the redundancy memory unit is not used. This eliminates the necessity of taking the sequence of the bit line numbers into account regardless of whether the product is a relief product or non-relief product. This facilitates the defect analysis. It is therefore possible to reduce the time necessary for the defect analysis.
Besides, arranging the column switch areas in mirror symmetry allows a reduction in the layout size of the column switch areas.
According to another aspect of the semiconductor memory of the present invention, in each of the sub memory units, the column switch circuits are arranged in a row in the wiring direction of the bit lines. In adjoining sub memory units within each of the main memory units, the column switch circuits are arranged such that the sequences of their corresponding data terminals' numbers are opposite to each other. Consequently, in two adjoining sub memory units of each main memory unit, the bit lines of one of the sub memory units are successively connected to the column switch circuits aligning in one direction while the bit lines of the other sub memory unit are successively connected to the column switch circuits aligning in the opposite direction. It is therefore possible to put the data terminal numbers of the bit lines in an identical sequence and form the column switch areas in mirror symmetry.
According to another aspect of the semiconductor memory of the present invention, the data bus lines are wired along each row of the column switch circuits aligning in the direction orthogonal to the wiring direction of the bit lines. Wiring the data bus lines for each row of the column switch circuits eliminates the necessity of intricately wiring the data bus lines in curves on the column switch circuits corresponding to the data terminals with the same numbers as that of the data bus lines. This facilitates the wiring layout of the data bus lines. Besides, the wiring area of the local data bus lines can be minimized.
According to another aspect of the semiconductor memory of the present invention, the column switch circuits have first and second transistors each. The drain of the first transistor is connected to any one of the data bus lines. The gate of the same receives a column selecting signal to be selected in accordance with an address. The gate of the second transistor is connected to any one of the bit lines. The drain of the same is electrically connected to a source of the first transistor during a read operation. Being connected at its gate to a bit line, the second transistor has the function of amplifying the voltage of the bit line. This system is commonly referred to as direct sense system. The present invention is also applicable to a semiconductor memory of direct sense system.
According to another aspect of the semiconductor memory of the present invention, the data bus lines transfer read data to be read from the memory cells and write data to be written to the memory cells. The number of data bus lines can be reduced by using the data bus lines for both read and write data. This facilitates the layout design. Besides, the layout area of the data bus lines can be reduced for smaller chip size.
According to another aspect of the semiconductor memory of the present invention, the column switch circuits have first through fourth transistors each. The drain of the first transistor is connected to any one of the data bus lines. The gate of the same receives a column selecting signal to

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