Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-12-26

2004-08-24

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S227000

Reexamination Certificate

active

06781869

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory.
2. Description of the Related Art
The technology for achieving high integration and low voltage of IC is developed, and with the development, an amount of charges held in the storage of a semiconductor memory decreases. As a result, in the semiconductor memory, there is a tendency for the following phenomenon, that is, a so-called soft error to easily generate. Namely, the negative and positive of charges held in the storage change by the influence of radioactive rays such as a ray and leak current. For this reason, in recent years, it has been deeply desired to provide a semiconductor memory, which is excellent for soft error resistance while achieving high integration and low voltage power.
In relation to the above matter, in a static RAM (hereinafter, referred to as SRAM) such that a written data is saved so long as a voltage source is supplied, it is general that an H-side memory node is connected to a voltage source at very low impedance, as compared with SRAM having a high resistance load type or TFT-type of memory cells. Thus, it has been known that SRAM having a bulk six-transistor (full CMOS) type of memory cells is excellent for soft error resistance. In the SRAM having full CMOS-type of memory cells, each memory cell has a structure of including an n-type bulk access transistor, an n-type bulk driver transistor and a p-type bulk load transistor by twos. However, in the SRAM having full CMOS-type of memory cells, a storage charge (voltage x capacitance) of memory cell decreases by low voltage and micro-fabrication of cell size in recent years; as a result, there is a problem such that a soft error is generated.
FIGS. 24A
to
24
D are views to explain a soft error generation process in a full CMOS-type of memory cell. The memory cell
90
has a general six-transistor cell structure.
FIG. 24A
shows a general data holding state in the memory cell
90
. In this state, cell nodes N
1
and N
2
are respectively held to H level and L level by a latch operation of inverter constituting by first and second load transistors
93
and
95
and first and second driver transistors
94
and
96
. In this case, the cell node N
1
at H level is connected to a power input terminal
91
to which a power supply voltage (VDD) is supplied, through the first load transistor
93
in ON-state; on the other hand, the cell node N
2
at L level is connected to a ground terminal
92
through the second driver transistor
96
in ON-state.
Then, as shown in
FIG. 24B
, a large charge instantaneously intrudes into the cell node N
1
at H level on the memory cell
90
in such data holding state. In this case, the cell node N
1
can not follow the drive to voltage level supplied from the power supply voltage (VDD) by the first load transistor
93
. As a result, the cell node N
1
is shifted to the L level.
Further, as shown in
FIG. 24C
, when the cell node N
1
is shifted to the L level, the cell node N
2
is driven to the voltage level supplied from the power supply voltage (VDD) by the second load transistor
94
. As a result, the second driver transistor
96
is changed over from ON-state to OFF-state.
Sequentially, the cell node N
2
is driven to the voltage level supplied from the power supply voltage (VDD), and thereby, as shown in
FIG. 24D
, the first driver transistor
95
is changed over from OFF-state to ON-state so that the cell node N
1
is driven to the ground level. In the above manner, the ground terminal
92
and the cell node N
1
are connected each other. As a result, the memory cell
90
keeps holding error data.
In order to prevent the generation of soft error as described above, in the SRAM having full CMOS-type of memory cells, predetermined measures must be carried out in design rule of 0.18 or less &mgr;m rule particularly in order to secure a predetermined or more soft error resistance. In the conventional case, the following matter has been known as one of measures for securing the soft error resistance carried out in the semiconductor memory. That is, a charge capacitance is added to the cell node.
For example, Japanese Patent laid-open publication 2001-77327 discloses the technology that, in the semiconductor memory having a plurality of memory cells, the capacitors of adjacent memory cells are formed in mutually different layer, and the adjacent forming regions of the capacitors overlaps with each other on plane, and thereby, a capacitor capacitance is secured much.
Moreover, Japanese Patent laid-open publication 8-236645 discloses the technology that, in the static type of memory cell, a GND line connected to a source region of drive MOSFET is arranged so as to cover a data-transfer MOSFET and the drive MOSFET, and source, channel and drain regions of load thin film transistor are formed on the upper layer of the GND line through an insulating film. Further, a power supply voltage line connected to the source region of the load thin film transistor is arranged in parallel to a word line, and the direction of the channel region of the load thin film transistor is formed in parallel to a bit line. Further, the drain region of the load thin film transistor is formed in a state of being bent into the word line direction and the bit line direction, and a static capacitance section is provided using the GND line and the bent drain region as facing electrodes.
However, the above-mentioned conventional technology has the following problem. More specifically, a charge capacitance is added to the cell node, and thereby, a cell area and the number of manufacturing processes increase, and further, the yield is reduced by the increase of the number of manufacturing processes. In particular, the SRAM having CMOS-type of memory cells has the structure in which six MOS transistors in total are laid out on the same plane, for this reason, the cell area becomes large as compared with SRAM having a high resistance load type of memory cells. Therefore, a reduction of the cell area is further desired.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory which can add a charge capacitance to a cell node without increasing a cell area, and is excellent for soft error resistance.
Further, it is another object of the present invention to provide a method for manufacturing a semiconductor memory which can reduce the number of manufacturing processes required for adding a charge capacitance to the cell node, and can prevent a reduction of yield by adding the charge capacitance.
A semiconductor memory of an aspect of the present invention includes a plurality of full CMOS-type of memory cells arranged in an array. Each of said memory cells includes six transistors(that is, first and second load transistors, first and second driver transistors and first and second access transistors), two cell nodes and insulating film and a conductive film. The first load transistor and the first driver transistor are connected in series between a power supply voltage line and a ground voltage line, and have a gate connected to a same line in common. The second load transistor and a second driver transistor are connected in series between the power supply voltage line and the ground voltage line, and have a gate connected to a same line in common. The first cell node connects an active region of said first load transistor to an active region of said first driver transistor and connects with each gate of said second load transistor and said second driver transistor. The second cell node connects an active region of said second load transistor to an active region of said second driver transistor and connects with each gate of said first load transistor and said first driver transistor. The first access transistor is connected between said first cell node and a first bit line, and has a gate connected to a word line. The second access transistor is connected between said second cell node and a second bit line in conjugate with said first bit line, and has a

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