Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-03-25
2004-03-16
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S196000
Reexamination Certificate
active
06707740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology for reducing power consumption of a semiconductor memory.
2. Description of the Related Art
FIG. 1
shows an outline of a general SDRAM (Synchronous DRAM) of a conventional art. The SDRAM includes a column decoder CDEC, a memory cell array ALY, a plurality of sense buffers SB, a command decoder CMD, a read control circuit RCNT, a data output circuit OUT and a plurality of input buffers BUF for receiving signals from the exterior. Although not shown in the drawing, the SDRAM includes a control circuit, a row decoder and the like which operate according to a row address.
The column decoder CDEC activates a column line selecting signal CL
1
(or CL
2
to CL
4
) according to a column address of an address signal ADD supplied from the exterior. The memory cell array ALY includes a plurality of memory cells MC and a plurality of sense amplifiers SA and column switches CSW which correspond to the memory cells MC. In the memory cell array ALY, read data DT which are read from the plurality of memory cells MC in parallel during read operation are respectively amplified in the sense amplifiers SA to become small-amplitude data signal. Thereafter, for example, the column line selecting signal CL
1
is activated, the corresponding column switch CSW turns on, and the data DT of the memory cell MC corresponding to the column line selecting signal CL
1
is transmitted to a local data bus line DB.
The command decoder CMD decodes a command signal CNT supplied from the exterior, and outputs a decoding result to the read control circuit RCNT. When the decoding result indicates a read command, the read control circuit RCNT activates a read control signal RDZ in synchronization with a clock signal CLK. Further, the read control circuit RCNT generates a control signal for operating the above-described column decoder CDEC. The sense buffers SB are activated in response to the read control signal RDZ. The sense buffers SB amplify the read data DT on the local data bus line DB up to a CMOS level, and output the amplified data to a common data bus line CDB. Namely, the sense buffers SB operate as read amplifiers for amplifying the read data DT further which are already amplified in the sense amplifiers SA.
The data output circuit OUT receives the read data DT through the common data bus line CDB, and outputs the received read data DT to the exterior in synchronization with an internal clock signal CLKZ which synchronizes with the clock signal CLK supplied from the exterior.
FIG. 2
shows burst read operation of the above-described SDRAM. In this example, a word line is already activated according to a row address signal in the first state of the timing chart, and data DT
1
to DT
4
which are read from the plurality of memory cells MC are respectively amplified by the sense amplifiers SA. A burst length is set to “4”. It should be mentioned that the burst length is a number of times of successively outputting the read data in one read operation. As will be described later, the read control circuit RCNT activates the read control signal RDZ the number of times corresponding to the burst length, and the sense buffers SB operate the number of times corresponding to the burst length so that the read data DT are sequentially outputted to the common data bus line CDB.
First, a read command RD and a column address (not shown) are supplied in synchronization with the zeroth clock signal CLK (FIG.
2
(
a
)). The read control circuit RCNT in
FIG. 1
controls the column decoder CDEC, and activates the column line selecting signal CL
1
which corresponds to the column address (FIG.
2
(
b
)). In response to the activation of the column line selecting signal CL
1
, the column switch CSW turns on, and the read data DT
1
is transmitted to the local data bus line DB (FIG.
2
(
c
)).
The read control circuit RCNT activates the read control signal RDZ in synchronization with the clock signal CLK to operate the sense buffers SB (FIG.
2
(
d
)). The sense buffers SB amplify the read data DT
1
on the local data bus line DB up to the CMOS level, and output the amplified data to the common data bus line CDB (FIG.
2
(
e
)). Since it is required for the sense buffers SB to drive the common data bus line CDB whose wiring length is large, it is necessary to speed up these operations and to increase these drivabilities. The data output circuit OUT outputs the read data DT received through the common data bus line CDB to the exterior in synchronization with the internal clock signal CLKZ (FIG.
2
(
f
)).
Thereafter, operations similar to the above are performed in the first to third clock cycles, and the read data DT
2
to DT
4
are sequentially outputted to the exterior. Namely, the read control signal RDZ is activated a number of times corresponding to the burst length, and the sense buffers SB perform amplifying operations this number of times.
As described above, each of the sense buffers SB is structured by a circuit operating at a high speed in order to amplify the small-amplitude data signal of the read data DT up to the CMOS level at a high speed. Further, since it is necessary for the sense buffers SB to output the amplified data to the common data bus line CDB having a large load, the sense buffers SB are designed so that these drivabilities are high enough. Hence, the sense buffers SB consume large current. Further, the same number of the sense buffers SB as a bit number of data terminals concurrently operate. Hence, power consumption of the SDRAM during the read operation is highly dependent on the power consumption of the sense buffers SB.
During the burst read operation, the sense buffers SB and their control circuit operate the number of times corresponding to the burst length. Hence, the power consumption increases further.
In general, measures have been taken so that the read data DT are transmitted to the data output circuit OUT at a high speed, such as increasing a wiring width of the common data bus line CDB, reducing its resistance, and the like. Alternatively, a buffer with a high drivability is inserted at the midpoint of the common data bus line CDB, thereby reducing a transfer time of the read data DT. However, these measures cause further increase in the power consumption.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory which can substantially reduce its power consumption during read operation as compared with a conventional art, and, more particularly, to reduce power consumption during burst read operation.
According to one of the aspects of the semiconductor memory of the present invention, a plurality of sense amplifiers amplify parallel read data from a plurality of memory cells, respectively.
A connection switching circuit connects the sense amplifiers to a predetermined read amplifier, according to an address. Switching the read data to one another before amplification by the read amplifiers allows read data to be first outputted during the burst read operation to be amplified by the read amplifier always having a higher drivability. Therefore, it is possible to shorten a read operation time and to reduce the power consumption, even in the semiconductor memory in which the output orders of read data are switchable according to addresses or operation modes.
A plurality of the read amplifiers amplify the read data amplified in the sense amplifiers up to predetermined logic levels, respectively. At least one of the read amplifiers has a higher drivability than those of the rest of the read amplifiers. The read amplifier having a higher drivability can drive the data bus lines at a higher speed than the rest of the read amplifiers. The read data amplified by the read amplifier having a higher drivability is transmitted to a data output circuit before the other read data, and hence it is possible to shorten the data read time. The drivability of the read amplifiers are easily adjusted by, for example, sizes, such as a gate width, of transistors cons
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