Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-12-04

2004-07-20

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S190000

Reexamination Certificate

active

06765817

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory suited for, for example, a mobile terminal which operates by a battery. More specifically, the present invention relates to a semiconductor memory, such as an SRAM (Static Random Access Memory), which realizes high-rate operation at low power supply voltage.
DESCRIPTION OF THE RELATED ART
As a technique related to this field, there has been known hitherto one described in the following document:
Shibata and Morimura, “0.25-&mgr;m SRAM Micro-Cell operating at 1V for Mobile Terminal”, pp. 1-8, Shingakugiho, ICD97-52 (1997-6), Journal of IEICE (Institute of Electronics, Information and Communication Engineers).
An SRAM is widely used as a cache memory for an ASIC (Application Specific IC) or the like which is used in a mobile terminal or the like. Since the mobile terminal or the like employs a battery as a power supply, low power supply voltage and low power consumption are required for the mobile terminal or the like. If power supply voltage is decreased, the operating rates of MOS transistors which constitute the SRAM decrease. In turn, when the threshold voltages of the MOS transistors are decreased to accelerate the respective operating rates, in a standby state, leak current caused by sub-threshold current increases, thereby disadvantageously increasing power consumption.
To solve these disadvantages, there is proposed an MTCMOS (Multi-Threshold CMOS) based on a CMOS (complementary MOS transistor) LSI technique, which can operate at low power supply voltage (e.g., 1V) when being active and which can prevent an increase in power consumption due to leak current in a standby state.
FIGS. 6A and 6B
show a conventional SRAM which utilizes the MTCMOS technique described in the above-cited document.
FIG. 6A
is a schematic block diagram showing the entire SRAM, and
FIG. 6B
is a circuit diagram showing the configuration of a memory cell and that of a peripheral circuit thereof.
As shown in
FIG. 6A
, this SRAM includes a memory cell array
10
consisting of high threshold voltage MOS transistors, and a peripheral circuit
20
consisting of low threshold voltage MOS transistors.
The memory cell array
10
is comprised of a plurality of word lines WLi and a plurality of bit line pairs BLj, /BLj (where “/” means inversion or low active) arranged to be orthogonal to the respective word lines WLi. Memory cells
11
ij
for data storage are connected to the intersections between the word lines and the bit line pairs, respectively.
The peripheral circuit
20
includes an address decoder
21
and an input/output circuit
22
.
The address decoder
21
is a circuit which decodes a row address in an address signal AD applied from the outside of the SRAM, and selects a corresponding word line WLi in the memory cell array
10
. The input/output circuit
22
is a circuit which decodes a column address in the address signal AD to output a column select signal/Yj, and which reads and writes data DA from and to the memory cells
11
ij
connected to the bit line pair BLj, /BLj selected by this column select signal/Yj in accordance with a read control signal/RE and a write control signal/WE, respectively.
The peripheral circuit
20
is connected to the power supply voltage VDD of a battery through a switch
23
consisting of a high threshold voltage MOS transistor. In a standby state, the switch
23
is controlled to be turned off using a sleep signal SL to thereby suppress the consumption of the battery caused by sub-threshold leak current. On the other hand, the memory cell array
10
is constantly turned on since the memory cell array
10
cannot be disconnected from the power supply during a standby state so as to hold the storage contents of the memory cells. Due to this, the MTCMOS technique is applied to the memory cell array
10
in order to suppress the sub-threshold leak current and to accelerate operation rate.
As shown in
FIG. 6B
, each memory cell
11
ij
in this memory cell array
10
includes a flip-flop FF consisting of high threshold voltage inverters L
1
and L
2
which hold data on nodes N
1
and N
2
. A high threshold voltage N channel MOS transistor Q
1
driven by the potential of the word line WLi connects the bit line BLj with positive phase to the node N
1
. A high threshold voltage N channel MOS transistor Q
2
driven by the potential of the same word line WLi connects the bit line /BLj with opposite phase to the node N
2
.
Further, the memory cell
11
ij
includes an acceleration circuit AC which encourages discharging the bit line pair BLj, /BLj and thereby accelerates read operation. The acceleration circuit AC consists of low threshold voltage N channel MOS transistors Q
3
to Q
6
. The transistors Q
3
and Q
4
are connected to the bit lines BLj and /BLj, respectively and driven by the potential of the word line WLi. The transistors Q
3
and Q
5
are connected in series and the transistors Q
4
and Q
6
are connected in series. One end of the transistors Q
5
and Q
6
are connected to each virtual ground line VGj arranged in parallel to the bit lines BLj. The transistors Q
5
and Q
6
are driven by the potentials of the nodes N
1
and N
2
, respectively.
One end of the virtual ground line VGj is connected to a ground voltage GND through a high threshold voltage N channel MOS transistor
31
j
. The transistor
31
j
is controlled to be turned on and off by the output signal of a NOR circuit
32
j
which NORs the read control signal/RE and the column select signal/Yj.
The operation of the memory cell
11
ij
shown in
FIG. 6B
will next be described.
During data write, when the word line WLi is selected to be set at “H” level, the transistors Q
1
to Q
4
are turned on and the data of the bit line data pair BLj, /BLj is held in the flip-flop FF. At this moment, the read control signal/RE is inactive and set at “H” level. Therefore, the output signal of the NOR circuit
32
j
is at “L” level and the transistor
31
j
is turned off. Accordingly, the virtual ground line VGj turns into a floating state and the transistors Q
3
and Q
4
in the acceleration circuit AC do not influence data write operation.
During data read, when the read control signal/RE is activated to be set at “L” level and the column select signal/Yj is selected to be set at “L” level, the level of the output signal of the NOR circuit
32
j
becomes “H” level. As a result, the transistor
31
j
is turned on and the virtual ground line VGj is connected to the ground voltage GND. If the word line WLi is then selected to be set at “H” level, the transistors Q
1
to Q
4
are turned on. At this moment, one of the nodes N
1
and N
2
is at “H” level, so that one of the transistors Q
5
and Q
6
is turned on.
For example, when the node N
1
is at “H” level and the node N
2
is at “L” level, the transistor Q
5
is turned off and the transistor Q
6
is turned on. As a result, not only the inverters L
1
and L
2
drive the bit line pair BLj, /BLj but also the low threshold voltage transistors Q
3
to Q
6
having high current driving abilities drive the bit line pair BLj, /BLj. Thus, read operation can be accelerated. That is, when the “H” level of the node N
1
and the “L” level of the node N
2
are to be read, the transistor Q
6
is turned on. Due to this, the potential of the bit line /BLj is decreased to the ground voltage GND through the transistors Q
4
, Q
6
and
31
j
, accelerating the read operation.
Further, in a standby state, the high threshold voltage transistor
31
j
is turned off by the output signal of the NOR circuit
32
j
and the leak current caused by the sub-threshold currents of the low threshold voltage transistors Q
3
to Q
6
is shut off, so that low power consumption can be realized.
The conventional memory cell, however, has the following disadvantages.
During data read, the transistor
31
j
is turned on, the virtual ground line VGj is connected to the ground voltage GND, charge from the acceleration circuit AC is discharged to the ground voltage GND through this transistor
31
j
and the read operatio

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