Semiconductor memory

Details Semiconductor memory Semiconductor memory

1997-06-30

1999-02-23

Dinh, Son T.

Harvesters

36518505, 36518511, G11C 1604

Patent

active

058751289

ABSTRACT:
In a semiconductor memory including NOR type cells in which memory cell transistors are located between adjacent bit lines and virtual ground lines, the connection pattern of bit line selecting transistors included, in each of adjacent bit line selection circuits SEL1 and SEL2, to bit line selecting lines, is inverted to that in an adjacent bit line selection circuit. When a memory cell transistor M05 is selected, D6 becomes the bit line and D5 becomes the virtual GND line. At this time, however, since D3 is brought to the precharge level, a current flows through the non-selected transistors M03 and M04 to the virtual GND line D5. But, since this current flows through the two non-selected transistors M03 and M04 to the virtual GND line D5, this current is smaller than the prior art semiconductor memory in which the current flows through only one non-selected transistor.

REFERENCES:
patent: 4597064 (1986-06-01), Giebel
patent: 5392233 (1995-02-01), Iwase
patent: 5448518 (1995-09-01), Jinbo
patent: 5583808 (1996-12-01), Brahbmhat
patent: 5748538 (1998-05-01), Lee et al.

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