Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-03-01

2003-06-24

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S230030, C365S051000

Reexamination Certificate

active

06584027

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having sense amplifiers.
2. Description of the Related Art
FIG. 1
shows a conventional DRAM memory core. The memory core is provided with four memory blocks BLK
0
-
3
. Each memory block BLK has two memory cell arrays ALY and a sense amplifier array RSA (RSA
0
-
3
) to be shared between these memory cell arrays ALY. The sense amplifier array RSA consists of, for example, 1024 sense amplifiers (not shown) which are arranged in the horizontal direction of the diagram.
The memory cell arrays ALY have a plurality of memory cells MC to be selected by word lines WL and bit lines BL (or /BL). The sense amplifier arrays RSA each have signal lines of first activating signals PSA (PSA
0
-
3
) and NSA (NSA
0
-
3
), a second activating signal /RCL (/RCL
0
-
3
), and a third activating signal WCL (WCL
0
-
3
) which are laid in the horizontal direction of the diagram. In the following description, the symbols of the signals (such as PSA, NSA, /RCL, and WCL) will be also used as symbols for the signal lines that transmit the respective signals.
The memory core also includes first sense amplifier control circuits C
1
(C
1
-
0
, C
1
-
1
, C
1
-
2
, C
1
-
3
) and second sense amplifier control circuits C
2
(C
2
-
0
, C
2
-
1
, C
2
-
2
, C
2
-
3
) corresponding to the respective sense amplifier arrays RSA, row decoders RDEC corresponding to the respective memory cell arrays ALY, and a column decoder CDEC.
The first sense amplifier control circuits C
1
activate the first activating signals PSA (PSA
0
-
3
) and NSA (NSA
0
-
3
) in accordance with an upper row address R
1
, R
0
. The activation of the first activating signals PSA and NSA activates latches (to be described later) of all the sense amplifiers in the corresponding sense amplifier arrays RSA. The second sense amplifier control circuits C
2
activate the second activating signals /RCL and the third activating signals WCL in accordance with the upper row address R
1
, R
0
.
The row decoders RDEC operate in accordance with a 3-bit row address RADD including the upper row address R
1
, R
0
, and select the word lines WL in accordance with a lower row address RADD. The column decoder CDEC activates column selecting signals CL (CL
0
,
1
, . . . ) in accordance with a column address CADD. The column selecting signals CL are signals common to the four memory blocks BLK
0
-
3
. The activation of the column selecting signals CL turns on predetermined column switches (to be described later) of sense amplifier arrays RSA that are activated by the first activating signals PSA and NSA. That is, the sense amplifiers are selected in accordance with the column selecting signals CL.
FIG. 2
shows the details of the sense amplifier array RSA
0
of FIG.
1
. The sense amplifier arrays RSA
1
-
3
have the same structure as that of the sense amplifier array RSA
0
.
FIG. 2
is rotated 90° relative to FIG.
1
.
The sense amplifier array RSA
0
has a plurality of sense amplifiers SA corresponding to the respective bit line pairs BL, /BL. Isolation gates for isolating the sense amplifiers SA from the memory cell arrays ALY are formed on both sides of the sense amplifiers SA (right and left in the diagram). The isolation gates are controlled by bit line selecting signals /SBTL and /SBTR, respectively. That is, the sense amplifier array RSA
0
is shared between the memory cell arrays ALY on both sides by means of the bit line selecting signals /SBTL and /SBTR.
Each sense amplifier includes a latch
2
, a read control circuit
4
, and a write control circuit
6
. The latch
2
is composed of two CMOS inverters having inputs and outputs connected to each other. When the first activating signals PSA
0
and NSA
0
are activated (high level and low level, respectively), the latch
2
is activated to amplify data on the bit line BL (or /BL) and latch the data amplified. The first activating signal lines PSA
0
and NSA
0
are laid common to all the sense amplifiers SA in the sense amplifier array RSA
0
. On this account, the first activating signal lines PSA
0
and NSA
0
have a great wiring length and high load capacitance. In read operations and write operations, the activation of the first activating signals PSA
0
and NSA
0
activates all the latches
2
in the sense amplifier array RSA
0
simultaneously.
The read control circuit
4
has an amplifying transistor
4
a
and a switching transistor
4
b
(column switch) for each bit line BL, /BL. Each amplifying transistor
4
a
is connected at its gate to the bit line BL (or /BL) and at its source to the second activating signal line /RCL
0
. Each switching transistor
4
b
is connected at its source to the drain of an amplifying transistor
4
a
, at its gate to the column selecting signal line CL, and at its drain to a read data bus line RDB
0
(or /RDB
0
). The second activating signal line /RCL
0
is laid common to the amplifying transistors
4
a
of all the sense amplifiers SA in the sense amplifier array RSA
0
. On this account, the second activating signal line /RCL
0
has a great wiring length and high load capacitance.
The amplifying transistors
4
a
have the function of amplifying read data received at their gates and outputting the resultant to their drains. Such a circuit system of sense amplifiers in which the gates are connected to bit lines is generally referred to as direct sense system. In the direct sense system, the bit lines BL and /BL are not directly connected to the read data bus lines RDB
0
and /RDB
0
. Therefore, even if the column selecting signal CL is activated before data read from the memory cells MC is amplified completely, the read operation will be performed properly without corruption of data on the bit lines BL and /BL. That is, it is suited to high-speed operation.
The write control circuit
6
has two switching transistors
6
a
and
6
b
in series for each bit line BL, /BL. Each switching transistor
6
a
is connected at one end to a write data bus line WDB
0
(or /WDB). Each switching transistor
6
b
(column switch) is connected at one end to the bit line BL (or /BL). The two gates of the switching transistors
6
a
and
6
b
are connected to the third activating signal line WCL
0
and the column selecting signal line CL (CL
0
-
1
), respectively. The third activating signal line WCL
0
is laid common to the switching transistors
6
a
of all the sense amplifiers SA in the sense amplifier array RSA
0
. On this account, the third activating signal line WCL
0
has a great wiring length and high load capacitance.
FIG. 3
shows the operations of the DRAM described above. In this example, the DRAM receives an active command ACTV from the exterior when in a standby state STBY, and then receives a read command READ and a write command WRITE to perform a read operation and a write operation in succession. After the write operation, the DRAM also receives a precharging command PRE from the exterior and precharges (equalizes) bit line pairs BL, /BL.
Initially, the active command ACTV and a row address RADD are supplied. A bit line resetting signal /BRS of the memory block BLK corresponding to the row address RADD turns to low level, releasing the precharge of the bit line pairs BL, /BL (FIG.
3
(
a
)). The row decoder RDEC of
FIG. 1
activates a word line WL in accordance with the row address RADD (FIG.
3
(
b
)). Due to the activation of the word line WL, data is read from the memory cells MC to the bit lines BL (or /BL) (FIG.
3
(
c
)).
Next, the first sense amplifier control circuit C
1
corresponding to the row address RADD activates the first activating signals PSA and NSA (FIG.
3
(
d
)). The first activating signal lines PSA and NSA are connected to the latches of all the sense amplifiers SA in the memory block BLK. Therefore, due to the activation of the first activating signal lines PSA and NSA, all the latches
2
in the memory block BLK start an amplifying operation, amplifying the voltage differences between the bit lines BL and /BL (FIG.
3
(
e
)). All the latc

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