Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-07-10

2003-03-04

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S155000, C365S156000, C365S159000

Reexamination Certificate

active

06529401

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and, in particular, to a memory cell structure having improvements in resistance to soft error of a MOS static RAM.
2. Description of the Background Art
As the miniaturization of memory cells proceeds, the following soft error problem becomes noticeable. Specifically, the data stored in a storage node is inverted due to electrons generated from alpha rays released from a package and neutron beams from outer space. Particularly, as power supply voltage is lowered, malfunction becomes more significant. Attempts to reduce soft error are being pursued.
FIG. 37
is a circuit diagram illustrating a structure equivalent to a SRAM memory cell disclosed in, for example, Japanese Patent No. 2589949. As shown in
FIG. 37
, a memory cell
100
is made up of PMOS transistors PT
1
and PT
2
, and NMOS transistors NT
5
to NT
8
, NT
11
, NT
12
, NT
21
and NT
22
.
The sources of the PMOS transistors PT
1
and PT
2
are both connected to a power supply voltage V
cc
. The drain of the PMOS transistor PT
1
is connected through a node
101
to the gate of the PMOS transistor PT
2
and to the gates of the NMOS transistors NT
21
and NT
22
. The drain of the PMOS transistor PT
2
is connected through a node
111
to the gate of the PMOS transistor PT
1
and to the gates of the NMOS transistors NT
11
and NT
12
.
The sources of the NMOS transistors NT
11
and NT
12
are both grounded. The drain of the NMOS transistor NT
11
is connected through the node
101
to the drain of the PMOS transistor PT
1
. The drain of the NMOS transistor NT
12
is connected through the nodes
101
and
102
to the drain of the PMOS transistor PT
1
.
The sources of the NMOS transistors NT
21
and NT
22
are both grounded. The drain of the NMOS transistor NT
21
is connected through the node
111
to the drain of the PMOS transistor PT
2
. The drain of the NMOS transistor NT
22
is connected through the nodes
111
and
112
to the drain of the PMOS transistor PT
2
.
The NMOS transistor NT
5
is interposed between a bit line BL
50
and the node
101
, and its gate is connected to a word line WL
50
. The NMOS transistor NT
6
is interposed between a bit line BL
60
and the node
101
, and its gate is connected to a word line WL
60
. The NMOS transistor NT
7
is interposed between a bit line BL
51
and the node
111
, and its gate is connected to the word line WL
50
. The NMOS transistor NT
8
is interposed between a bit line BL
61
and the node
101
, and its gate is connected to the word line WL
60
.
In such a configuration, the word line WL
50
or WL
60
is brought into the active state and the NMOS transistors NT
5
and NT
6
, or the NMOS transistors NT
6
and NT
8
are brought into the on state, thereby to provide access to the nodes
101
and
111
, each being a storage node. This enables to obtain the data from the paired bit lines BL
50
and BL
51
or the paired bit lines BL
60
and BL
61
.
In this configuration, a NMOS driver transistor that is usually made up of a single NMOS transistor is divided into two NMOS transistors (which is divided into the NMOS transistors NT
11
and NT
12
, and NT
21
and NT
22
).
In order to divide the storage node serving as the drain of the PMOS transistor PT
1
(PT
2
) into the node
101
(
111
) and the node
102
(
112
), the NMOS transistor NT
11
(NT
21
) and the NMOS transistor NT
12
(NT
22
) are oppositely disposed so as to interpose therebetween an N well region where the PMOS transistor PT
1
is to be formed.
Therefore, the N well region prevents that a depletion region on the opposite side of the N well region is adversely affected by electrons or holes generated from energy particles colliding with one side of the N well region. This enables to lower incidence of soft error.
However, even with the foregoing SRAM memory cell, a reduction in soft error is insufficient. Further, there is the problem that the circuit configuration is complicated by using two driver transistors, although it can be generally configured by using one.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a semiconductor memory having a memory cell containing first and second inverters subjected to cross connection, a first conductivity type being defined by first kind, and a second conductivity type being defined by second kind, is characterized in that: the first inverter consists of a first field effect transistor of the first kind and a first field effect transistor of the second kind; that the second inverter consists of a second field effect transistor of the first kind and a second field effect transistor of the second kind; and that the first and second field effect transistors of the first kind are disposed in separate first and second well regions of the second kind, respectively.
According to a second aspect of the invention, the semiconductor memory of the first aspect is characterized in that an output part of the first inverter includes a connecting part between one electrode of the first field effect transistor of the first kind and one electrode of the first field effect transistor of the second kind, an input part thereof includes a connecting part between a control electrode of the first field effect transistor of the first kind and a control electrode of the first field effect transistor of the second kind; an output part of the second inverter includes a connecting part between one electrode of the second field effect transistor of the first kind and one electrode of the second field effect transistor of the second kind, and an input part thereof includes a connecting part between a control electrode of the second field effect transistor of the first kind and a control electrode of the second field effect transistor of the second kind; that the memory cell further includes: (i) a third field effect transistor of the first kind, one electrode of which is connected to a first storage terminal electrically connected to the output part of the first inverter and the input part of the second inverter, and the other electrode of which is connected to a first bit line, and a control electrode of which is connected to a word line; and (ii) a fourth field effect transistor of the first kind, one electrode of which is connected to a second storage terminal electrically connected to the output part of the second inverter and the input part of the first inverter, and the other electrode of which is connected to a second bit line, and a control electrode of which is connected to a word line; and that the third and fourth field effect transistors of the first kind are disposed in second and first well regions of the second kind, respectively.
According to a third aspect of the invention, the semiconductor memory of the second aspect is characterized in that the respective one electrodes in the first to fourth field effect transistors of the first kind are disposed separately.
According to a fourth aspect of the invention, the semiconductor memory of the second aspect is characterized in that: the first and third field effect transistors of the first kind and the first field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of the word line; and that the second and fourth field effect transistors of the first kind and the second field effect transistor of the second kind are arranged in an approximately straight line along the direction of formation of the word line.
According to a fifth aspect of the invention, the semiconductor memory of the first aspect is characterized in that the first and second field effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of the memory cell.
According to a sixth aspect of the invention, the semiconductor memory of the second aspect is characterized in that the third and fourth field effect transistors of the first kind are arranged so as to be point symmetry with respect to the central point of the memory

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