Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-28
2003-09-16
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030
Reexamination Certificate
active
06621750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having a redundancy circuit for relieving defects in memory cells,
2. Description of the Related Art
In general, semiconductor memories have redundancy circuits to relieve lattice defects in the substrates and defects that occur in the fabrication processes. For example, DRAMs and the like are provided with redundancy memory cell rows aside from regular memory cell rows. Semiconductor memories of this type, provided with redundancy memory cell rows, have fuse arrays for storing the addresses of memory cell rows that contain defective memory cells.
When some memory cells are defective, fuses in the fuse arrays are blown in advance according to the addresses of the memory cell rows containing the defective memory cells. The blowing of fuses disables the defective memory cell rows and enables the redundancy memory cell rows instead when the semiconductor memories are powered on. That is, the defective memory cells are relieved. In this way, the redundancy memory cells are used to relieve defective memory cells for the sake of improved yields.
As described above, the fuse arrays are used to replace defective memory cell rows with the redundancy memory cell rows. Consequently, in semiconductor memories provided with a plurality of memory blocks having redundancy memory cell rows, the fuse arrays are necessary for the respective memory blocks. Hence, the fuse arrays can increase in number when the semiconductor memories have greater numbers of memory blocks.
The fuses are blown by the irradiation of laser beams, and thus require considerably greater layout areas than such devices as transistors. Besides, adjoining fuses must be well spaced from each other. The number of fuse arrays therefore has a significant impact on the chip size of the semiconductor memories. If the fuse arrays are reduced in number so as to prevent the increase in chip size, there occur unrelievable memory blocks. This results in a problem of lower yields.
In addition, the fuse size depends chiefly on the precision of the laser irradiation apparatus and hardly on the semiconductor fabrication processes. Thus, the fuse size will not decrease even if the transistor structures get finer with advancing process technology. In other words, the further the process technology advances, the greater the fuse arrays become in area with respect to the chip area.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory, which can be improved in relief efficiency with no increase of, fuse arrays.
Another object of the present invention is to reduce the chip size of a semiconductor memory having a redundancy circuit.
According to one of the aspects of the semiconductor memory of the present invention, the semiconductor memory includes a plurality of memory blocks operating at different timings from one another, a redundancy memory circuit, and a redundancy control circuit. Each of the memory blocks has a plurality of memory cell rows containing memory cells and a redundancy memory cell row containing redundancy memory cells. The redundancy memory cell row relieves a defective memory cell row which includes a defective memory cell out of the memory cell rows. The redundancy memory circuit stores a defect address (address information) indicating the defective memory cell row existing in any one of the memory blocks into its first memory unit. The first memory unit is composed of, for example, a plurality of fuses for storing respective bits of the defect address.
The redundancy control circuit receives the address information, and disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables the redundancy memory cell row instead of the defective memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables the redundancy memory cell rows instead of these memory cell rows. Consequently, when the redundancy memory circuit contains a defect address, riot only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. The redundancy memory circuit can thus be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. Despite the reduction in the number of redundancy memory circuits, there occurs no unrelievable memory block. In addition, when the redundancy memory circuit is composed of fuses, it is possible to significantly reduce the layout area thereof. As a result, the semiconductor memory can be reduced in chip size.
According to another aspect of the semiconductor memory of the present invention, the memory cell rows each include a selecting line for selecting the memory cells. The redundancy control circuit includes a first receiver circuit and a first switching circuit, which are formed in one of the memory blocks, and a second receiver circuit and a second switching circuit, which are formed in the rest of the memory blocks, respectively. The first receiver circuit receives the address information stored in the first memory unit firstly and directly. The first switching circuit disables one of the memory cell rows according to the address information received. The second receiver circuit receives the address information transmitted through the selecting line of the memory block, which has firstly and directly received the address information. The second switching circuit disables the memory cell rows according to the address information received.
In this way, the address information is transmitted by using the selecting lines of the memory blocks which are used in normal memory operations. The use of the existing signal lines eliminates the need to provide new wiring for transmitting the address information. Consequently, applying the present invention to any semiconductor memory causes no increase in the number of lines or increase in the chip size resulting from increased wiring
According to another aspect of the semiconductor memory of the present invention, the address information transmitted to each of the memory blocks including the second receiver circuit is transmitted to another one of the memory blocks including the second receiver circuit through the selecting line. Thus, the use of the existing selecting lines allows the address information to be transmitted to all the memory blocks.
According to another aspect of the semiconductor memory of the present invention, the first receiver circuit, which receives the address information first, decodes the address information with its redundancy decoder. The decoding result (address information) is transmitted to the second receiver circuit through the selecting line. The address information received by the second receiver circuit is held in a latch. Hence, in the memory blocks which include the second, receiver circuits, the defective memory cell row can be disabled by using the stored address information after the address information is transmitted to a second receiver circuit of another memory block. In other words, the second receiver circuit need hot receive the address information directly from the redundancy memory circuit. As for the first receiver circuit, it need not store the address information since it always receives the address information from the redundancy memory circuit.
According to another aspect of the semiconductor memory of the present invention, the first and second switching circuits operate as transmission paths during a predetermined period at power-up, thereby transmitting the address information to the selecting line. Subsequently, the first and second switching circuits operate as switches, disabling the defective memory cell row according to the address information. That is, the first and second switching circuits can serve both as the tran
Fujioka Shin-ya
Hara Kota
Mori Katsuhiro
Okuyama Yoshiaki
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Hoang Huan
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