Semiconductor memory

Details Semiconductor memory Semiconductor memory

2000-11-29

2002-06-18

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185200

Reexamination Certificate

active

06407957

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having a memory cell, and more particularly to a technology for reading data stored in a memory cell at high speed.
2. Description of the Related Art
Among the known semiconductor memories having memory cells are flash memories, EPROMs, DRAMs, and SDRAMs.
FIG. 1
schematically shows a read-operation-related circuit in a flash memory.
A flash memory includes an address buffer
2
, an X-decoder
4
, a memory cell array
6
, a Y-decoder
8
, a sense amplifier
10
, an output buffer
12
, and a control circuit
14
.
The address buffer
2
receives an address signal from the chip exterior, and outputs the received address signal to the X-decoder
4
and the Y-decoder
8
. The X-decoder
4
and the Y-decoder
8
select a word line WL and a bit line BL corresponding to the address signal, respectively. The Y-decoder
8
also has a switching function of connecting the bit line BL to the sense amplifier
10
. The memory cell array
6
has a plurality of memory cells MC arranged in a matrix. The sense amplifier
12
amplifies read data transmitted from a memory cell MC through the bit line BL and the Y-decoder
8
, and outputs-the resultant to the output buffer
12
. The output buffer
12
outputs the amplified read data to the chip exterior. The control circuit
14
receives a control signal from the chip exterior, and controls the address buffer
2
, the sense amplifier
10
, and the output buffer
12
in accordance with the received control signal.
Though not shown specifically, a multi-bit product having a plurality of input/output terminals includes a plurality of Y-decoders
8
, sense amplifiers
10
, and output buffers
12
corresponding to the input/out put terminals. Here, a plurality of memory cells MC are selected by predetermined word lines WL, and a plurality of sense amplifiers
10
corresponding to the individual input/output terminals are operated. Then, the read data (in a plurality of bits) is simultaneously output from the output buffers
12
.
FIG. 2
shows the essential parts of a flash memory having its memory cell array divided into a plurality of blocks BLK), BLK
1
, BLK
2
, and so on. This flash memory has n input/output terminals.
Each block BLK has a plurality of Y-decoders
8
corresponding to the individual input/output terminals. The Y-decoders
8
in the same block BLK are connected to sense amplifiers
10
through data line switches
16
and data lines DATAB (
0
) to DATAB (n−1), respectively. In other words, through the intervention of the data lines DATAB, the plurality of blocks BLK share the sense amplifiers
10
that are formed for the individual input/output terminals. The data line switches
16
are controlled by block decoders
18
. The data lines DATAB (
0
) to DATAB (n−1) are wired next to and in parallel with each other. These data lines DATAB (
0
) to DATAB (n−1) constitute data bus DBUS.
In this flash memory, read data to be output from a predetermined block BLK is selected by a block decoder
18
and transmitted to the data bus DBUS. The read data transmitted to the data bus DBUS is amplified by the sense amplifiers
10
.
FIG. 3
shows an example of a sense amplifier
10
.
A sense amplifier
10
has an inverter
10
a
, an nMOS transistor
10
b
, and a load
10
c
. The input of the inverter
10
a
and the source of the nMOS transistor
10
b
are connected to a data line DATAB. The output of the inverter
10
a
is connected to the gate of the nMOS transistor
10
b
so that the inverter
10
a
and the nMOS transistor
10
b
form a feedback loop. The drain of the nMOS transistor
10
b
and one end of the load
10
c
are connected to an output node OUT. The other end of the load
10
c
is connected to a power supply line VCC. This type of sense amplifiers
10
is generally referred to as “cascode type.”
FIG. 4
shows voltage variation on a data line DATAB in read operations.
Initially, a bit line BL and the data line DATAB are charged up. The bit line BL and the data line DATAB rise from 0 V to approximately 1 V in voltage. Then, in accordance with the state stored in the memory cell MC, electric current flows through the bit line BL and the data line DATAB to cause voltage variation on the data line DATAB.
When the memory cell MC stores “0,” no current flows through the bit line BL and the data line DATAB. The inverter
10
a
shown in
FIG. 3
becomes low in output voltage, and the nMOS transistor
10
b
becomes high in source-to-drain resistance. As a result, a current supply from the load
10
c
turns the output node OUT to high level.
When the memory cell MC stores “1,” a current flows through the bit line BL and the data line DATAB. The data line DATAB drops in voltage, making the output voltage of the inverter
10
a
high. The nMOS transistor
10
b
becomes low in source-to-drain resistance. As a result, a current supplied from the load
10
c
is fed to the data line DATAB through the nMOS transistor
10
b
, thereby effecting the feedback control on the inverter
10
a
. This turns the output node OUT to low level.
Here, the voltage difference on the data line DATAB between the “0” read and the “1” read is as small as several tens of milli-volts.
By the way, the sense amplifiers
10
described above need to detect a small voltage on the data lines DATAB. To prevent a malfunction of the sense amplifiers
10
, the data lines DATAB must be wired so as not to be affected by the coupling from other adjacent signal lines. This measure is important particularly when the sense amplifiers
10
are shared among a plurality of blocks BLK as described above, since the data lines DATAB become greater in wiring length.
Specifically, the layout design is made with consideration given to the following respects:
(1) Prevent signals that vary during a read operation (clock signal and the like) from adjoining the data lines DATAB
(2) Provide greater wiring spacings between the data lines DATAB and other adjacent signals
(3) Shield the data lines DATAB
The above-mentioned respect (2), however, brings about a problem of increased layout areas.
FIG. 5
shows an example of layout taking the above-mentioned respect (3) into account.
In this example, ground lines VSS are laid out along both sides of the data bus DBUS. The ground lines VSS (0 V) have no voltage variation during read operations.
FIG. 6
shows a read operation by the circuit shown in FIG.
5
.
A difference in potential between a data line DATAB and a ground line VSS increases as the data line DATAB rises in voltage. An electric charge corresponding to the potential difference is stored into a parasitic capacitance formed between the two lines. The outer the data line DATAB, the greater the amount of charge stored is. Thus, the outer data lines DATAB (
0
) and DATAB (n−1) adjacent to the ground lines VSS tend to lag in rise.
Meanwhile, the inner data lines DATAB (
1
) to DATAB (n−2) have smaller potential differences with their adjacent data lines DATAB. This means less transfer of charge to parasitic capacitances formed among these data lines DATAB (
1
) to DATAB (n−2). As a result, the inner data lines DATAB (
1
) to DATAB (n−2) rise at high speed and at the same timing.
The read time (access time) is determined according to the data established the latest in the multi-bit read data. For this reason, the shielding of the data lines DATAB by the ground lines VSS has been an obstacle to performing high-speed operations.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory capable of reading data stored in a memory cell at high speed.
According to one of the aspects of the semiconductor memory in the present invention, the semiconductor memory includes a plurality of data lines, a sense amplifier, and dummy data lines. The data lines are wired next to each other, and transmit data read from memory cells. The sense amplifier receives the data and outputs an amplified signal. The dummy data lines are laid out alon

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