Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-06-01

2002-11-26

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S189011, C365S189110

Reexamination Certificate

active

06487138

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory having fast access to a built-in memory cell and particularly concerns a dynamic random access memory.
BACKGROUND OF THE INVENTION
Conventionally, in a semiconductor memory having fast access to a built-in memory cell, particularly in a dynamic random access memory (hereinafter, abbreviated as DRAM), a voltage VPP is usually used as a voltage of a word line. The voltage VPP is higher than a voltage for driving a bit line or a voltage for driving a control circuit.
Such a conventional semiconductor memory will be described.
FIG. 18
is a circuit diagram showing a conventional semiconductor memory. In
FIG. 18
, reference numeral
1
denotes a memory array, reference numeral
2
denotes a word driver, reference numeral
3
denotes a level shifter constituting the word driver
2
, reference numeral
4
denotes a first-stage driver where a high voltage VPP is supplied, reference numeral
5
denotes second-stage drivers which receive a high voltage VPP and are driven by the first-stage driver
4
, reference numeral
6
denotes word lines, reference numeral
7
denotes a memory cell, reference numeral
8
denotes a sense amplifier, reference numeral
9
denotes a sense amplifier driver, reference numeral A
1
denotes a first address signal, and reference numeral A
2
denotes a second address signal.
The level shifter
3
level-converts the first address signal Al, the output is inputted to the first-stage driver
4
, and word-line select signals WD and /WD, which are the outputs of the first-stage driver
4
, are inputted to the second-stage drivers
5
. The second-stage drivers
5
are driven by the second address signal A
2
and the outputs are connected to the word lines
6
. Further, the word line
6
is connected to the memory cell
7
. The memory cell
7
is connected to the sense amplifier
8
via a bit line, and the sense amplifier
8
is connected to the sense amplifier driver
9
.
In response to the output of the level shifter
3
driven by the first address signal Al, the first-stage driver
4
outputs the word line select signals WD and /WD, and the second-stage drivers
5
receiving the word-line select signals WD and /WD drives the word lines
6
.
Such a conventional semiconductor memory is configured such that the word lines
6
are driven by a two-stage configuration including the first-stage driver
4
and the second-stage drivers
5
. Moreover, a number of two-stage drivers
5
are connected to the word line select signals WD and /WD outputted from the first-stage driver
4
, and P-channel transistors
10
and
11
connected to the word-line select signal WD are large in size. Consequently, the load of the first-stage driver
4
is large and requires a long time to drive the word lines
6
.
Additionally, between the word line
6
and a power source VPP supplied to the word line
6
, two stages of the P-channel transistor
12
and the P-channel transistor
11
are connected in series, and the impedance rises. Therefore, it takes a longer time to drive the word lines
6
.
DISCLOSURE OF THE INVENTION
The present invention is achieved to solve the above conventional problem. The object of the present invention is to provide a semiconductor memory by which a word line can be driven faster than the conventional art and a layout area can be reduced so as to miniaturize a chip in case where the chip is formed as a semiconductor integrated circuit.
The semiconductor memory of the present invention, in which a memory array comprising a plurality of bit line pairs driven by a signal based on data, a plurality of word lines driven by a signal based on an address, and memory cells placed on the intersections thereof is supplied with a signal based on the data and address, the plurality of bit line pairs and the plurality of word lines are driven so that the data is written into the memory cells via the plurality of bit line pairs, the semiconductor memory comprising: a plurality of level shifters for producing a first select signal, which. vary in voltage level between a first source voltage and a ground in response to a first address signal, and are activated at a ground level to select the word lines; a plurality of word drivers for driving a selected one of the word lines in response to the first select signal; each of said word drivers comprising: a first transistor of a first conductivity type inserted between an associated word line and a power line for supplying the first source voltage; and a second transistor of a second conductivity type inserted between the associated word line and the ground. The first select signal is inputted to a gate of the first transistor via a switch controlled by a second address signal different from the first address signal, and to a gate of the second transistor.
Further, the semiconductor memory of the present invention is configured that the level shifter further produces a second select signal which a polarity opposite to the first select signal, a voltage level of the second select signal varying between the first source voltage and the ground, wherein each of the word drivers further comprises: a third transistor of the first conductivity type having source connected to the source line, a drain connected to a gate of the first transistor, and a gate connected to said associated word line; a fourth transistor of the first conductivity type having a source connected to the source line, a drain connected to the gate of the first transistor, and a gate receiving the second select signal; and a fifth transistor of the second conductivity type having a source connected to the ground, a drain connected to the associated word line, and a gate receiving a third address signal with a polarity opposite to the second address signal. The switch comprises: a sixth transistor of the second conductivity type having a source receiving the first select signal, a gate receiving the second address signal, and a drain connected to the gate of the first transistor.
According to the above configurations, when driving the word line, it is possible to reduce impedance between the word line and the first power source, thereby driving the word line at high speeds.
Moreover, the semiconductor memory of the present invention is characterized in that the third transistor of the first conductivity type has a gate width one tenth of or less than that of the first transistor of the first conductivity type.
Additionally, the semiconductor memory of the present invention is characterized in that the fourth transistor of the first conductivity type has a gate width one tenth of or less than that of the first transistor of the first conductivity type.
According to the above configurations, it is possible to switch the word drivers at high speeds, thereby driving the word line at high speeds.
Also, the semiconductor memory of the present invention is characterized by arranging the plurality of word drivers such that the word lines selected and driven by the same level shifter from the plurality of level shifters are not adjacent to each other.
According to the above configuration, the sixth transistor of the second conductivity type can be formed to be of a small size, reducing a layout area of the word drivers.
Moreover, the semiconductor memory of the present invention is characterized by supplying the first power source exclusively from the outside of the chip.
According to the above configuration, it is possible to eliminate the need for mounting an exclusive booster circuit, thereby reducing a chip area.
Furthermore, the semiconductor memory of the present invention is characterized in that the first power source is supplied by boosting a second power source with a booster circuit provided in the chip, the second power source supplying a voltage lower than that of the first power source to another circuits such as a control circuit.
Additionally, the semiconductor memory of the present invention is characterized in that the first power source is the same as a power source supplied to an

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