Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-09-28

2002-12-17

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S145000

Reexamination Certificate

active

06496428

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory having a redundancy circuit for relieving defects in memory cell regions. In particular, the present invention relates to a nonvolatile semiconductor memory having a redundancy circuit.
2. Description of the Related Art
In general, semiconductor memories are broadly classified into volatile semiconductor memories such as a DRAM (Dynamic Random Access Memory) which require power to hold data, and nonvolatile semiconductor memories such as a flash memory/EEPROM (Electrical Erasable Programmable Read Only Memory) which require no power to hold data. The performance of a semiconductor memory is often expressed in memory capacity, access speed, and power consumption.
DRAMs are mainly used for computer's main storage as large-capacity high-speed semiconductor memories. Because of being volatile, however, DRAMs require refresh operations to hold data, and thus are high in power consumption.
Flash memories/EEPROMs are mainly used for file systems, memory cards, portable equipment, and the like as large-capacity, low-power-consumption nonvolatile semiconductor memories. Flash memories/EEPROMs, however, require extremely longer time for data write.
Meanwhile, ferroelectric memories having memory cells composed of ferroelectric capacitors have been recently developed as semiconductor memories that combine the advantages of DRAMs and flash memories/EEPROMs. Ferroelectric memories can hold data even without power supply, by utilizing residual polarization that remains even after the voltages applied to their ferroelectric capacitors are removed.
Ferroelectric memories are increasing in memory capacity year after year, and their substitution for flash memories is under consideration. The rise in memory capacity tends to increase chip size. On this account, defect-relieving technologies (redundancy circuit technologies) for ferroelectric memories have been studied recently. Among known redundancy circuit technologies for ferroelectric memories is one disclosed in Japanese Unexamined Patent Application Publication No. 2000-215687, for example.
The ferroelectric memory disclosed in this publication contains ordinary memory cells, redundancy memory cells, and memory cells for redundancy files for retaining the column addresses of memory cells to be relieved as replacement information. These memory cells, redundancy memory cells, and memory cells for redundancy files are connected to common word lines. That is, in read operations and write operations, the memory cells, redundancy memory cells, and memory cells for redundancy files are simultaneously selected in accordance with the activation of the word lines. Each single redundancy memory cell is formed for, e.g., eight ordinary memory cells.
The ferroelectric memory has a logic circuit for decoding replacement information (defect addresses) read from the memory cells for redundancy files to generate decoding signals corresponding to each column address, and a logic circuit for generating the OR logic of these decoding signals. Column switches for the memory cells are deselected in response to any of the decoding signals. Column switches for the redundancy memory cells are selected in response to the OR logic of the decoding signals. That is, in response to the replacement information, access to defective memory cells is disabled and access to redundancy memory cells is enabled to relieve the defective memory cells.
FIG. 1
shows an overview of a ferroelectric memory having a redundancy circuit of this type.
In the diagram, the ferroelectric memory has a plurality of memory blocks MB. The memory blocks MB each have a word driver
10
, a plate driver
12
, a column control circuit
14
, a memory cell region MCR, a redundancy memory cell region RCR, and a redundancy information region DCR.
The word driver
10
supplies a voltage to a predetermined word line WL according to a row address. The plate driver
12
supplies a voltage to a predetermined plate line PL according to the row address. The column control circuit
14
outputs column selecting signals CL and a redundancy column select signal RL to the memory cell region MCR and the redundancy memory cell region RCR, respectively, in accordance with a column address as well as relief information (relief address information and the like) output from the redundancy information region DCR. The activation of the column selecting signals CL turns on the column switches (not shown) in the memory cell region MCR. The activation of the redundancy column selecting signal RCL turns on the redundancy column switches (not shown) in the redundancy memory cell region RCR.
The memory cell region MCR is composed of memory cells MC to be used in normal operations. The redundancy memory cell region RCR is composed of memory cells MC for relieving defective memory cells. The redundancy information region DCR is composed of memory cells MC for indicating the locations of the defective memory cells. The memory cells MC in the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are connected to common word lines WL and plate lines PL In read operations and write operations, memory cells in the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are simultaneously selected in accordance with the activation of a word line WL and a plate line PL. In other words, memory cells MC that are activated between a word line WL and a plate line PL become accessible.
For example, if a word line WL and a plate line PL are activated to read relief information showing relief from a memory cell MC in the redundancy information region DCR, the column select signals CL are inactivated and the redundancy select signal RCL is activated. The inactivation of the column selecting signals CL turns off the column switches to disable the access to the defective memory cells MC in the memory cell region MCR (marked with crosses in the diagram). The activation of the redundancy column selecting signal CL turns on the redundancy column switches to enable the access to the memory cells MC in the redundancy memory cell region RCR (marked with circles in the diagram). That is, the defective memory cells MC are replaced with the normal memory cells MC to relieve the memory cells MC.
In the ferroelectric memory cell disclosed in the above-mentioned publication, the memory cells, redundancy memory cells, and memory cells for redundancy files are selected at the same time. Therefore, it is of importance to the high speed execution of read/write operations how to operate the column switches quickly in response to replacement information (column address). In the ferroelectric memory described above, however, the column switches for the redundancy memory cells are selected in accordance with the OR logic of the decoding signals which select the column switches for the ordinary memory cells. Accordingly, there has been a problem that the column switches for the redundancy memory cells delay in operation, with slower access time particularly during redundancy operations. The access time of a semiconductor memory is determined by the access time of the slowest memory cells. As a result, the access time of the redundancy memory cells makes the actual access time of the chip. Besides, there has been a problem that a rise in the circuit scale of the redundancy circuit can increase the chip size.
In each memory block MB of the ferroelectric memory shown in
FIG. 1
, the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are successively arranged next to the word driver
10
and the plate driver
12
. That is, the redundancy information region DCR is placed far from the word driver
10
and the plate driver
12
.
Word lines WL and plate lines PL typically have parasitic resistance and parasitic capacitance. Thus, the farther from the word driver
10
and the plate driver
12
the memory cells

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