Semiconductor memory

Static information storage and retrieval – Read/write circuit – Bad bit

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36523006, G11C 700

Patent

active

058019995

ABSTRACT:
A redundant semiconductor memory capable of functioning normally on the whole even if two column (or row) lines do not function normally. The semiconductor memory includes primary and secondary selection circuits, primary and secondary switchover circuits, and (N+2) memory cell groups. The primary switchover circuit receives a decoded address signal of N bits for selecting one memory sell group, and outputs to the secondary switchover circuit a signal of (N+1) bits which is generated by inserting a bit into a position of the inputted decoded address signal specified by the primary selection circuit. The secondary switchover circuit outputs to the memory cell groups a signal of (N+2) bits which is generated by inserting a bit into a position of the inputted signal specified by the secondary selection circuit.

REFERENCES:
patent: 5323348 (1994-06-01), Mori et al.
patent: 5394368 (1995-02-01), Miyamoto
patent: 5572482 (1996-11-01), Hoshizaki

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