Semiconductor memory

Details Semiconductor memory Semiconductor memory

2008-05-13

2008-05-13

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S042000, C714S048000, C714S719000, C714S766000, C714S800000, C365S201000

Reexamination Certificate

active

07373564

ABSTRACT:
A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

REFERENCES:
patent: 5903582 (1999-05-01), Miyazaki
patent: 6466490 (2002-10-01), Nagai et al.
patent: 7032142 (2006-04-01), Fujioka et al.
patent: 05-054697 (1993-03-01), None
IBM Technical Disclosure Bulletin NN79054871, “Mechanism for Checking Parity And Error Checking And Correction Functions in Processors And Processor Linked Subsystems”, May 1979, vol. 21, issue 12.
IBM Technical Disclosure Bulletin NB8908370, “Integrated Error Correction/Test Memory Feature”, Aug. 1989, vol. 32, issue 3B.

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