Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2011-07-12
2011-07-12
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
07978550
ABSTRACT:
A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy program circuit, second defect position information indicating a position of a second defective regular memory cell being programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell.
REFERENCES:
patent: 5550394 (1996-08-01), Sukegawa et al.
patent: 7281155 (2007-10-01), Eto et al.
patent: 2002/0031017 (2002-03-01), Yumoto
patent: 2008/0126876 (2008-05-01), Lee
patent: 2000-100191 (2000-04-01), None
patent: 2001-006389 (2001-01-01), None
Arent & Fox LLP
Fujitsu Semiconductor Limited
Phung Anh
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