Semiconductor memory

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36523003, 371 102, G11C 700

Patent

active

051576287

ABSTRACT:
A semiconductor memory in which a normal memory area is divided into a plurality of divided memory areas, a data buffer is provided for each of the divided memory areas, the bit lines of each divided memory area is connected via column selector to a data buffer corresponding to the divided memory area, a buffer changeover switching means is connected between each data buffer and the data bus, a column accessing is made by turning the buffer changeover switching means in a predetermined sequence while said column selector is controlling by output signals of the column decoder decoding the column address signals, is disclosed.
The above mentioned semiconductor memory is so designed that, for rescuing the bit in trouble without uselessly increasing the area, a redundancy memory area and a redundancy data buffer are provided which are connected via the redundancy select switching means, said redundancy select switching means is turned on by an address comparator circuit when the column address in trouble coincides with the column address signal, and that the redundancy data buffer is connected to the data bus when the buffer changeover switching means connected to the data buffer corresponding to the divided memory area containing the bit in trouble in turned on and the redundancy select switching means is turned on, with the normal memory area side being further disconnected from the data bus at least during the reading operation.

REFERENCES:
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4885721 (1989-12-01), Katanosaka
patent: 4890262 (1989-12-01), Hashimoto et al.
patent: 4905192 (1990-02-01), Nogami et al.

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