Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-09
2001-04-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S051000, C365S063000
Reexamination Certificate
active
06222784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the layout of a semiconductor memory, particularly relates to the layout of a dynamic random access memory (DRAM) comprising a memory cell array in which memory cells are arranged in a matrix shape and a sense amplifier array which is disposed adjacent to the memory cell array.
2. Description of the Related Art
In recent years, a DRAM is required to operate increasingly at high speed. Various propositions have been put forth to realize this requirement.
For example, there is a proposition that wirings each having resistance lower than that of word lines are arranged adjacent to the word lines, and the word lines and the wirings having low resistance (hereinafter referred to as low resistance wirings) are connected to one another in word line shunt areas provided at given intervals, so that signals applied to the word lines are transmitted at high speed.
Japanese Patent Laid Open Publication No. 9-139477 published May 27, 1997 has put forth a proposition of the layout of word line shunt areas in a memory cell array in the interests of high speed operation.
If a desired word line is selected out of a plurality of word lines in a memory cell array, data in the memory cell connected to the selected word line is applied to a bit line. Data applied to the bit line is amplified by a given sense amplifier of a plurality of sense amplifiers in a sense amplifier array disposed adjacent to the memory cell array. The amplified data is applied to a data bus which is arranged in the sense amplifier array.
Considering the delay of a signal applied to the word line, a plurality of word line shunt areas are arranged in predetermined positions in the memory cell array. Such a delay of signal applied to the word line has received widespread attention.
However, the delay of a control signal for controlling a plurality of sense amplifiers has not received widespread attention so far, and hence no effective proposition has been put forth.
As miniaturization and high capacity of a DRAM have progressed in recent years, a sense amplifier circuit and a method of controlling it becomes complex. Accordingly, a load applied to sense amplifier control signal lines each transmitting a control signal for controlling a plurality of sense amplifiers becomes large. As a result, there occurs a delay of the control signal for controlling the sense amplifiers. It seems that this delay causes a serious problem when miniaturization and high-capacity of a DRAM increasingly progress.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor memory capable of efficiently controlling the delay of a control signal for controlling sense amplifiers without extensively changing a currently-used fabricating process.
It is another object of the invention to provide a semiconductor memory for improving capacitive balance of a data bus pair without extensively changing a currently-used fabricating process.
It is still another object of the invention to provide a semiconductor memory capable of realizing the reduction of power supply noise and improvement of latch-up tolerance without extensively changing a currently-used fabricating process.
It is more still another object of the invention to provide a semiconductor memory capable of miniaturizing a sense amplifier control portion and of reducing the number of sense amplifier control signal lines without extensively changing a currently-used fabricating process.
To achieve these objects, a typical invention of this application comprises as follows.
A semiconductor memory includes a plurality of bit line pairs which are arranged in parallel with one another, and a plurality of sense amplifiers each connected to ends of each bit line pair for amplifying the potential between the bit line pairs, wherein a sense amplifier corresponding to a given bit line pair of the plurality of bit line pairs is not arranged so as to secure a given area in the arrangement of a plurality of sense amplifiers.
The semiconductor memory includes sense amplifier control signal lines for transferring control signals for controlling the plurality of sense amplifiers and sense amplifier control signal lines having low resistance (hereinafter referred to as low resistance sense amplifier control signal lines) and extending substantially in parallel with the sense amplifier control signal lines and having resistance which is lower than that of the sense amplifier control signals, and sense amplifier signal line connecting portions formed in the given area for connecting the sense amplifier control signal lines and the low resistance sense amplifier control lines.
The semiconductor memory includes a power supply wiring formed in a semiconductor circuit board for supplying power, wherein the power supply wiring and the semiconductor circuit board are connected to each other in the given area.
The semiconductor memory further includes a data bus pair to which a voltage which is amplified by the plurality of sense amplifiers is applied, wherein the data bus pair have crossing portions in the given area.
The semiconductor memory further includes second sense amplifier control signal lines for transferring the control signals and a buffer circuit formed in the given area for connecting between the sense amplifier control signal lines and the second the sense amplifier control signal lines.
With such construction set forth hereinbefore, it is possible to provide a semiconductor memory capable of achieving the above objects without extensively changing a currently-used fabricating process.
REFERENCES:
patent: 5255231 (1993-10-01), Oh
patent: 5359216 (1994-10-01), Coleman et al.
patent: 5483495 (1996-01-01), Fukuda
patent: 5886939 (1999-03-01), Choi et al.
patent: 6084816 (2000-07-01), Okamura
patent: 6-318391 (1994-11-01), None
patent: 7-135301 (1995-05-01), None
patent: 9-139477 (1997-05-01), None
patent: 10-93048 (1998-04-01), None
Elms Richard
Jones Volentine, LLC
Nguyen Vanthu
OKI Electric Industry Co., Ltd.
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