Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1998-12-14
2001-04-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S200000, C365S230030
Reexamination Certificate
active
06212118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a rewriting operation of a memory cell and a relieving operation of a defective memory cell in a semiconductor memory.
2. Description of Related Art
Many proposals have been made in a technology in which, when a defective memory cell is found out in a semiconductor memory, a suitable redundant memory cell is efficiently selected in place of the defective memory cell, and information to be stored in the defective memory cell is actually stored in the selected redundant memory cell, in order to avoid the above mentioned defect and to elevate the yield of production in the semiconductor memory.
For example, Japanese Patent Application Pre-examination Publication No. JP-A-03-104096 (an English abstract of JP-A-03-104096 is available from the Japanese Patent Office and the content of the English abstract of JP-A-03-104096 is incorporated by reference in its entirety into this application) proposes a semiconductor memory configured to prevent a plurality of output bits from failing simultaneously in order to elevate a bit relieving effect in a redundancy operation thereby to elevate reliability of the semiconductor memory. For this purpose, in a semiconductor memory of a m-bit input/output construction having a plurality of cell array columns, a plurality of sense amplifier columns, a row selection circuit provided for the plurality of sense amplifier columns, and a column selection circuit provided in common to the plurality of sense amplifier columns, the sense amplifier columns and cell array columns are divided into “m” groups in each of which a redundant sense amplifier and a redundant cell array are provided, and simultaneously, the column selection circuit is divided into “m” groups in each of which a redundant column selection circuit is provided.
Japanese Patent Application Pre-examination Publication No. JP-A-05-258591 (an English abstract of JP-A-05-258591 is available from the Japanese Patent Office and the content of the English abstract of JP-A-05-258591 is incorporated by reference in its entirety into this application) proposes a defective relieving method in which a redundant word line and an address comparing circuit/redundant decoder circuit are provided for each memory cell array block, and an address of a word line connected to a defective memory cell is programmed in an address comparing circuit provided in any memory cell block other than the memory cell array block including the defective memory cell, so that a defective word line is replaced by a redundant word line of the memory cell array block including the address comparing circuit thus programmed.
However, in technologies developed in this field of art including the above mentioned technologies, since it is a fundamental practice to select one word line, when an active operation such as a reading and a writing is executed, and when a rewriting operation called a refreshing is executed in a memory needing the refreshing, it is not possible to efficiently select a redundant circuit. With increase of memory cell arrays, since the number of word lines connected to the column selection line is increased, a load capacitance of the column selection line becomes large, resulting in an increased consumed current and in a lowered processing speed.
Here, a semiconductor memory capable of efficiently switch to a redundant circuit for a short time, is desired.
One example of the semiconductor memory is a synchronous DRAM having a construction as shown in
FIGS. 4 and 5
.
As shown in
FIGS. 4 and 5
, the semiconductor memory includes a plurality of memory cell arrays (for example, MAR
0
to MAR
3
), each of which includes a main word line and two sub-word lines associated thereto, a plurality of memory cells connected to each of the sub-word lines being connected to the same bit line of the same sense amplifier in the same sub-word line set, and being alternately connected to the other bit line of the same sense amplifier in an adjacent other sub-word line set.
Now, a detailed construction of the above mentioned semiconductor memory will be described with reference to
FIGS. 4
to
7
.
FIG. 4
is a block diagram illustrating one example of the above mentioned prior art synchronous DRAM, and
FIG. 5
is a block diagram illustrating the construction of the memory cell arrays MAR
0
to MAR
3
shown in FIG.
4
.
In addition,
FIG. 6
is a circuit diagram illustrating one example of the sub-word line driver circuit SWD shown in
FIG. 5
, and
FIG. 7
is a circuit diagram illustrating one example of the replacement row address comparing circuit RED shown in FIG.
4
. Incidentally, in the following description, for convenience of description it is assumed that the shown synchronous DRAM comprises four memory cell arrays, and the number of memory cells activated when a refresh command is inputted is four times the number of memory cells activated when an active command is inputted.
Furthermore, it is also assumed that when the refresh command is inputted, the main word lines M
00
to M
17
in all the memory cell arrays MAR
0
to MAR
3
are individually activated one by one. In
FIG. 4
, each of the memory cell arrays MAR
0
to MAR
3
includes a plurality of memory cells, and the memory cell arrays MAR
0
to MAR
3
operate independently of each other.
In the following, the construction of each memory cell array will be described. In
FIG. 5
, Reference Signs XD
00
to XD
17
designate main word line decoders, each of which is selected by a portion of an internal row address signal XI so as to drive a corresponding main word line M
00
to M
17
.
Reference Signs RAD
00
to RAD
11
designate power supply line driving circuits, each of which is also selected by a portion of the internal row address signal XI so as to supply a power supply voltage to a power supply voltage supplying line RAI
00
to RAI
11
.
On the other hand, Reference Sign SWD designates sub-word line driving circuits, each of which connected to a corresponding main word line M
00
to M
17
and a corresponding power supply voltage supplying line RAI
00
to RAI
11
. When the corresponding main word line and the corresponding power supply voltage supplying line are selected, the sub-word line driving circuit SWD drives an associated sub-word line S
0000
to S
1007
, and when at least one of the corresponding main word line and the corresponding power supply voltage supplying line is not selected, the sub-word line driving circuit SWD deactivates the associated sub-word line. Furthermore, Reference Sign RSWD designates redundant sub-word line driving circuits, each of which connected to a corresponding redundant main word line RXD
0
to RXD
7
and a corresponding power supply voltage supplying line RAI
00
to RAI
11
. When the corresponding redundant main word line and the corresponding power supply voltage supplying line are selected, the redundant sub-word line driving circuit RSWD drives an associated redundant sub-word line RS
00
to RS
17
, and when at least one of the corresponding redundant main word line and the corresponding power supply voltage supplying line is not selected, the redundant sub-word line driving circuit RSWD deactivates the associated redundant sub-word line.
Referring to
FIG. 6
which is a circuit diagram illustrating one example of the sub-word line driver circuit SWD shown in
FIG. 5
, the main word line M
00
is connected to a source of each of first and second transistors. The first transistor having the source connected to the main word line M
00
, has a gate connected to the power supply voltage supplying line RAI
00
, and a drain connected to a drain of a third transistor having a gate connected to another power supply voltage supplying line RAIB
00
and a source connected to ground. The second transistor having the source connected to the main word line M
00
, has a gate to a high potential and a drain connected to a gate of a fourth transistor having a source connected to the power supply volt
Elms Richard
NEC Corporation
Nguyen Vanthu
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