Semiconductor memory

Details Semiconductor memory Semiconductor memory

1986-03-25

1988-04-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365230, G11C 700

Patent

active

047363444

ABSTRACT:
A refresh arrangement is provided for a dynamic RAM wherein each time a refresh address counter performs a predetermined plurality of steps of increment operations, an address switching circuit is switched to specified refresh addresses held in an address storage circuit to provide addresses of memory cells having inferior data retention times. In this way the memory cells with inferior data retention times can be refreshed much more frequently than memory cells with normal data retention times.

REFERENCES:
patent: 4333167 (1982-06-01), McElroy
patent: 4360903 (1982-11-01), Plachno et al.
patent: 4376988 (1983-03-01), Ludwig et al.
M. Taniguchi et al., "M 5K 4164S with Built-In Refresh Function", Denshi Gijutsu (Electronics Technology)" vol. 23, No. 3, pp. 30-33 (no publication date available).

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