Semiconductor memory

Details Semiconductor memory Semiconductor memory

1985-08-05

1987-09-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365189, G11C 700

Patent

active

046929010

ABSTRACT:
A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

REFERENCES:
patent: 4061908 (1977-12-01), de Jonge et al.
Session X: Nonvolatile Memories, S. Tanaka et al., 1984 IEEE International Solid-State Circuits Conference, pp. 148 & 149, "A Programmable 256K CMOS EPROM with On-Chip Test Circuits".

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