Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-12-26
1993-11-23
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
36523006, G11C 2900
Patent
active
052650570
ABSTRACT:
There is provided a semiconductor memory including a plurality of word lines, a plurality of bit lines intersecting the word lines, and a memory cell array having memory cells arranged at respective intersections of the word lines and bit lines. Word line selecting circuits select the word lines in accordance with an address signal and word line driving circuits are connected to the word lines for driving selected word lines. Selective stress applying circuitry selectively applies stress, during a stress test, to word lines in one of a plurality of word line groups into which all word lines are classified. The selective stress applying circuits includes an arrangement of MOS transistors and pads for applying stress to a word line group during the stress test.
REFERENCES:
patent: 4349895 (1982-09-01), Isogai
patent: 4951259 (1990-08-01), Sato
patent: 4972372 (1990-11-01), Ueno
patent: 5086413 (1992-02-01), Tsuboi
patent: 5161121 (1992-11-01), Cho
Furuyama Tohru
Noji Hiroyuki
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Zarabian A.
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