Semiconductor memory

Static information storage and retrieval – Systems using particular element – Capacitors

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365187, 365150, G11C 700

Patent

active

058416900

ABSTRACT:
A semiconductor memory in which integration is enhanced is provided. An NMOS transistor Qn1 has a gate connected to a write word line WWLn, a source connected to a write bit line WBLn, and a drain connected to a node N1. An NMOS transistor Qn2 has a gate connected to a read word line RWLn and a source connected to a read bit line RBLn. An NMOS transistor Qn3 has a gate connected to the drain of the NMOS transistor Qn1, a source connected to a ground level, and a drain connected to the drain of the NMOS transistor Qn2. An NMOS transistor Qn4 has a gate connected to a ground level, a source connected to the source of the NMOS transistor Qn3, and a drain connected to the drain of the NMOS transistor Qn1. The NMOS transistor Qn4 is kept off so that the drain of the NMOS transistor Qn1 is dielectrically isolated from the source of the NMOS transistor Qn3.

REFERENCES:
patent: 4308594 (1981-12-01), Jiang
patent: 4534017 (1985-08-01), Thomas et al.
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 5377142 (1994-12-01), Matsumura et al.

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