Semiconductor memory

Static information storage and retrieval – Read/write circuit – Differential sensing

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365210, 36523006, G11C 1140

Patent

active

049929860

ABSTRACT:
A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 4825418 (1989-04-01), Itoh et al.
IBM Tech. Dis. Bul., vol. 24, No. 9, Feb. 1982, p. 4800, "Folded Bit Line Connection to Sense Latch", L. Arzubi.

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