Semiconductor memories with refreshing cycles

Details Semiconductor memories with refreshing cycles Semiconductor memories with refreshing cycles

2007-12-18

2007-12-18

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S154000, C365S189020

Reexamination Certificate

active

11514648

ABSTRACT:
The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing data stored in the array of storage cells are either true or inverted, a plurality of read-toggle drivers coupled on a plurality of data output paths for inverting the data outputs only when the mode bit indicates that the array of storage cells are storing inverted data, and a plurality of write-toggle drivers coupled on a plurality of data input paths for inverting the data inputs only when the mode bit indicates that the array of storage cells are storing inverted data and for writing back inverted data into the array of storage cells during a refreshing cycle.

REFERENCES:
patent: 6665224 (2003-12-01), Lehmann et al.
patent: 6731528 (2004-05-01), Hush et al.
G. Chen, “Dynamic NBTI of PMOS Transistors and Its Impact on Device Lifetime”, IEEE Electron Device Letters, vol. 23, No. 12, Dec. 2002.

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