Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2007-07-03
2007-07-03
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257SE29085
Reexamination Certificate
active
10540261
ABSTRACT:
An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain induction porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.
REFERENCES:
patent: 5221413 (1993-06-01), Brasen et al.
patent: 5458755 (1995-10-01), Fujiyama et al.
patent: 6180497 (2001-01-01), Sato et al.
patent: 6309945 (2001-10-01), Sato et al.
patent: 6313014 (2001-11-01), Sakaguchi et al.
patent: 6350703 (2002-02-01), Sakaguchi et al.
patent: 6448155 (2002-09-01), Iwasaki et al.
patent: 6468663 (2002-10-01), Sato et al.
patent: 6468923 (2002-10-01), Yonehara et al.
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 6649492 (2003-11-01), Chu et al.
patent: 6712288 (2004-03-01), Yanagita et al.
patent: 6720237 (2004-04-01), Iwasaki et al.
patent: 6828214 (2004-12-01), Notsu et al.
patent: 6890835 (2005-05-01), Chu et al.
patent: 6953948 (2005-10-01), Sakaguchi
patent: 7017830 (2006-03-01), Yanagita et al.
patent: 2003/0119280 (2003-06-01), Lee et al.
patent: 2003/0230778 (2003-12-01), Park et al.
patent: 2005/0280119 (2005-12-01), Momoi et al.
patent: 1 248 294 (2002-10-01), None
patent: 7-302889 (1995-11-01), None
patent: 11-195562 (1999-07-01), None
patent: 2002299261 (2002-10-01), None
patent: 2003-78118 (2003-03-01), None
patent: 2003-78140 (2003-03-01), None
patent: 2003-178977 (2003-06-01), None
patent: 2003-282463 (2003-10-01), None
patent: 2003-282464 (2003-10-01), None
patent: 2004-342975 (2004-12-01), None
patent: 533501 (2003-05-01), None
Machine translation of JP 2003-282464, Oct. 2006 cited by applicant.
Michael I. Current, et al. “Atomic-layer Cleaving with SiGe Strain Layers for Fabrication on Si and Ge-rich SOI Device Layers”, IEEE International SOI Conference, Oct. 2001, pp. 11-12.
Shin-ichi Takagi, “Metal-Oxide-Semiconductor (MOS) device technologies using Si/Ge heretointerfaces”, Oyo Buturi, vol. 72, No. 3, pp. 284-290, 2003.
T.A. Langdo, et al., Appl. Phys. Lett., vol. 56, No. 4, pp. 4256-4258 (2003).
D.J. Godbey, et al., Appl. Phys. Lett., vol. 56, No. 4, pp. 373-379 (1990).
D. Ferijoo, et al., J. Electro. Mat., vol. 23, No. 6, pp. 493-496 (1994).
A.H. Krist, et al., Appl. Phys. Lett., vol. 58, No. 17, pp. 1899-1901 (1991).
Ikeda Hajime
Nishida Shoji
Notsu Kazuya
Sakaguchi Kiyofumi
Sato Nobuhiko
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Jackson Jerome
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