Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-07
2010-02-23
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07669173
ABSTRACT:
A method of making a semiconductor device is disclosed. A target mask pattern is provided which includes features to be exposed on the mask, and features to be non-exposed on the mask. The to be exposed features are fractured by searching for geometries on the target mask pattern that meet one or more conditions, identifying mask pattern structures to be fractured, fracturing the identified pattern structures according to a fracture instruction list, creating a set of mask exposure patterns, exposing the mask to the mask exposure pattern, and developing the mask.
REFERENCES:
patent: 5808892 (1998-09-01), Tu
patent: 6523162 (2003-02-01), Agrawal et al.
patent: 6737199 (2004-05-01), Hsieh
patent: 6767674 (2004-07-01), Carpi
patent: 6887630 (2005-05-01), Luttrell
patent: 2005/0091632 (2005-04-01), Pierrat et al.
Garbowski Leigh Marie
Infineon - Technologies AG
Slater & Matsil L.L.P.
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