Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-10-25
2003-09-02
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06614050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor manufacturing apparatus, and relates in particular to a semiconductor manufacturing apparatus concerning a series of processes for manufacturing a semiconductor product.
2. Description of the Prior Art
Conventional semiconductor production is centered around the mass production of a small variety of devices, mainly memories and general-purpose logic products. Currently, small jobs for the production of specific types of devices, products that incorporate a system, such as ASICs, which are designs specifically adapted to fulfill the application needs of certain customers or to provide products that customers have expressed a need for, can only performed at intervals between the processing devoted to the mass production of standard devices. However, a system-on-silicon arrangement has recently been developed, and the production of product types where entire systems are mounted on single chips gradually increasing. While conventionally there are no memory-mounted semiconductor products, where memory is mounted on logic devices, techniques for mounting both logic circuits and memory on the same chip are requisite if an entire system is to be mounted on a single chip.
For the manufacture of semiconductor devices today, when the emphasis is on the production of a small variety of products, because of expansions in the sizes of substrates and reductions in the sizes of wiring, increases in the number of chips that can be obtained from a single substrate has contributed to a reduction in manufacturing costs. Thus, the current substrate size is approaching 300 mm, and as a result of means developed to reduce the size of wiring, all companies are now able to attain wire sizes down to 0.18 &mgr;m.
For ASICs, gate array devices and cell base devices are the primary types produced, and while bases can be used in common, for the gate array devices, wiring must be so arranged that the needs of a variety of customers can be satisfied.
For a gate array ASIC, a common base is used and only the wiring must be arranged so as to provide a design that matches the requests of customers; however, since the flexibility available with the design is small, as system sizes increase, so too do the difficulties encountered in fabricating devices that can provide the performances customers demand. Thus, it has been found that when designing an ASIC, a cell base device must be employed. But although with a cell base device the same base can be commonly employed, for this kind of ASIC, a designer must start at the very beginning.
While there are some ASIC products that are fabricated by employing mass production methods, generally, an ASIC is a device that is specially prepared for a single customer, quite unlike a general-purpose product, so that mass production is required for only a few such devices.
In an ordinary process used for the manufacture of semiconductor devices, several tens of silicon substrates are employed as a set (generally called a batch or a lot, and hereinafter referred to as a batch) that must be processed at each step.
Among the product types encountered in small scale production are many products for which the need can be satisfied merely by employing a single silicon substrate as a batch. In this case, several substrates are normally employed as a batch during the manufacturing process.
For large scale production, at least 1000 silicon substrates (20 to 25 batches) for one product type are delivered to a manufacturing line every month.
In the manufacture of semiconductors, the process performed to diffuse an impurity throughout a substrate and the wiring process are the primary operations, and the lithography process and the etching process for partly performing diffusion are associated operations.
A failure during the process can occur as a result, for example, of the performance of excessive or unsatisfactory etching. The occurrence of this phenomenon is due to the difference in an etching condition, or to the deposition of a film that is either too thick or too thin.
A characteristic failure is one that occurs due to a difference in the actual density or the depth of an impurity, attained during the diffusion process, that differs from a design value, or one that is due to an increase in the capacity between wires because they are too thick or to an increase in the resistance in wires because they are too thin.
Generally, these failures are roughly sorted into systematic failures and random failures.
For the large scale production of a small variety of devices, to prevent failures during the individual procedures, a shift away from a central value for a design is monitored either every several batches or each batch. Therefore, for an important procedure, several monitoring substrates are inspected before each batch, or are added to and are processed with batches as they are conveyed along the manufacturing line. However, as the substrate size increases, the system soon becomes too large for the collective manufacturing of semiconductor devices using batch units, and variances in a batch can not be absorbed. Therefore, the employment of production systems for the processing of individual substrates (hereinafter referred to as single wafer processing) has increased. In this case, a monitoring substrate is also employed and inspected for each batch.
As one consequence of a reduction in the sizes of wiring lines, a problem has arisen in that there has been an increase in the failures that are caused by particles (dust) contamination, and since the performance of inspections during the processing contributes to dust contamination, the practice is gradually falling into disuse.
The current semiconductor manufacturing process is performed by using a sheet called a process management slip on which a series of processes are written. Entries on a process management slip describe both a process objective (e.g., a thermally oxidized film one micron thick) and a process condition (e.g., stream oxidization at a ratio of 1 to 1 at a temperature of 1400 degrees for two hours) selected from a recipe that is contained in a correlation table of process conditions and results. When an experiment is conducted for a wafer in the same initial state as one that was used for the preparation of a recipe, and the state of an apparatus that is used is the same as that of the apparatus used for the preparation of the recipe, the same results are accordingly obtained.
However, the semiconductor manufacturing process consists of many steps, and individual wafers have their own processing histories. Thus, the initial state of a wafer supplied for processing is not always the same as that of a wafer used for the preparation of a recipe.
In addition, the internal temperature, the residual gas density, the vacuum level, the amount of energy to be exerted, and the extraneous matter that accumulates on the inner wall of an apparatus gradually vary in consonance with an increase in the number of processed wafers, the number of wafers that are handled at the same time, and the shape of a pattern. Therefore, relative to the processing capacity of an apparatus, the obtained results generally differ, even when the processing is performed under the same conditions as those specified by a standardized recipe. Thus, while a high quality product can be produced if a circuit margin is large, if a high-speed operating circuit is included, the size of a circuit margin is reduced and failures may occur as a result of even a very small procedural error.
Furthermore, the results provided by a process can not be evaluated until an electric test is conducted for a final product, a package into which a chip has been incorporated, so that an extended period of time is required before a failure can be found.
Thus, for products fabricated using large scale production, since a procedure is employed for the processing of a large number of batches before an evaluation of the results can be obtained, many failures occur.
And as for product
Tsujide Tohoru
Yamada Keizo
Fab Solutions, Inc.
Hayes & Soloway P.C.
Niebling John F.
Stevenson André C
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