Semiconductor layout structure for ESD protection circuits

Details Semiconductor layout structure for ESD protection circuits Semiconductor layout structure for ESD protection circuits

2007-07-03

2007-07-03

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S360000, C257SE29181

Reexamination Certificate

active

11152440

ABSTRACT:
A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

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