Semiconductor layer formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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C438S200000

Reexamination Certificate

active

07056778

ABSTRACT:
A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.

REFERENCES:
patent: 5461243 (1995-10-01), Ek et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5759898 (1998-06-01), Ek et al.
patent: 5846857 (1998-12-01), Ju
patent: 5943565 (1999-08-01), Ju
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6124627 (2000-09-01), Rodder et al.
patent: 6259138 (2001-07-01), Ohtani et al.
patent: 6339232 (2002-01-01), Takagi
patent: 6369438 (2002-04-01), Sugiyama et al.
patent: 6465316 (2002-10-01), Hattori et al.
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 6562703 (2003-05-01), Maa et al.
patent: 6583437 (2003-06-01), Mizuno et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6638802 (2003-10-01), Hwang et al.
patent: 6709909 (2004-03-01), Mizuno et al.
patent: 6723541 (2004-04-01), Sugii et al.
patent: 6743651 (2004-06-01), Chu et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6833332 (2004-12-01), Christiansen et al.
patent: 6855436 (2005-02-01), Bedell et al.
patent: 6881632 (2005-04-01), Fitzgerald et al.
patent: 2001/0048119 (2001-12-01), Mizuno et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0034529 (2003-02-01), Fitzgerald et al.
patent: 2003/0040160 (2003-02-01), Huang et al.
patent: 2004/0175872 (2004-09-01), Yeo et al.
patent: 2004/0242006 (2004-12-01), Bedell et al.
patent: 2004/0259334 (2004-12-01), Bedell et al.
patent: 2000243946 (1999-12-01), None
patent: WO 02/33746 (2002-04-01), None
patent: WO 02/45156 (2002-06-01), None
patent: WO 02/45156 (2002-06-01), None
Jung et al., “Implementation of Both High-Hole and Electron Mobility in Strained Si/Strained Si1-yGeyon Relaxed Si1-xGex(x<y) Virtual Substrate,”IEEE Electron Device Letters, vol. 24, No. 7, Jul. 2003, pp. 460-462.
Lee et al., “Sub-30 nm P+ abrupt junction formation in Strained Si/Si1-xGexMOS device,”Technical Digest of the International Electron Devices Meeting, Dec. 8, 2002, pp. 379-381.
LeGoues et al., “Kinetics and Mechanism of Oxidation of SiGe: Dry Versus Wet Oxidation,”Applied Physics Letters, Feb. 13, 1989, vol. 54, No. 7, pp. 644-646.
LeGoues et al., “Oxidation Studies of SiGe,”Journal of Applied Physics, Feb. 15, 1989, vol. 65, No. 4, pp. 1724-1728.
Lim, Y. S. et al., “Dry Thermal Oxidation of a Graded SiGe Layer”,Applied Physics Letters, vol. 79, No. 22, Nov. 26, 2001, pp. 3606-3608.
Sawano et al., “Relaxation Enhancement of SiGe Thin Layers by Ion Implantation into Si Substrates,”IEEE, 2002, pp. 403-404.
Tezuka et al., “Dislocation-free Formation of Relaxed SiGe-on-insulator Layers,”Applied Physics Letters, May 13, 2002, vol. 80, No. 19, pp. 3560-3562.
Tezuka, T. et al., “Fabrication of Strained Si on an Ultrathin SiGe-on-insulator Virtual Substrate with a High-Ge Fraction”,Applied Physics Letters, vol. 79, No. 12, Sep. 17, 2001, pp. 1798-1800.
Tezuka et al., “Ultrathin Body SiGe-on-Insulator pMOSFETs with High-Mobility SiGe Surface Channels,”IEEE Transactions on Electron Devices, vol. 50, No. 5, May 2003, pp. 1328-1333.
Vyatkin et al., “Ion Beam Induced Strain Relaxation in Pseudomorphous Epitaxial SiGe Layers,”IEEE, 2000, pp. 70-72.
Chi et al., “Electrically active defects in surface preamorphized and subsequently RTP-annealed Si and the effect of titanium silicidation,”Proc. 1998 5th International Conference on Solid-State and Integrated Circuit Technology, Oct. 21, 1998, Beijing, China, p. 324-327.
Fahey et al., “Point defects and dopant diffusion in silicon,”Reviews of Modern Physics, Apr. 1989, vol. 61, No. 2, pp. 289-384.

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