Semiconductor latches and SRAM devices

Details Semiconductor latches and SRAM devices Semiconductor latches and SRAM devices

2006-02-14

2006-02-14

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S066000

Reexamination Certificate

active

06998722

ABSTRACT:
A new Static Random Access Memory (SRAM) cell using a restoring device and a strong inverter is disclosed. An SRAM cell comprises a strong inverter and a strong access transistor constructed on a high-mobility semiconductor substrate layer. An N to 1 programmable multiplexer positioned above the inverter provides the input to said strong inverter from N available discrete voltage levels. A high mobility conducting path is used to read data quickly, while very small programmable elements vertically integrated in one or more planes increase the storage density at no extra area penalty. N data values are stored in one latch location, reducing memory area and cost significantly without sacrificing on time to access the stored data.

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