Semiconductor latches and SRAM devices

Details Semiconductor latches and SRAM devices Semiconductor latches and SRAM devices

2003-04-14

2004-12-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257SE27098

Reexamination Certificate

active

06828689

ABSTRACT:

BACKGROUND
The present invention relates to semiconductor latches and Static Random Access Memory (SRAM) devices.
A latch is a data storage unit in a semiconductor device comprising of two inverters. An inverter has an input and an output having a voltage of opposite polarity to said input. The inverter is connected between a system power voltage level and system ground voltage level. Two such inverters connected back-to-back have self sustaining voltages at their inputs and outputs. A static random access memory (SRAM) device is a type of semiconductor memory device that has low power consumption and fast access time relative to a dynamic random access memory (DRAM) device. An SRAM cell comprises a latch and one or more access devices. The latch stores binary data, and the access device provides the capability to read and write data into the latch. Multiple access devices provide multiple access paths to read and write the single latch data. An SRAM memory device is essentially an array of SRAM cells. They are classified by the type of inverter in the latch, by the total transistor count in the SRAM cell and by the number of access devices to configure the latch. Typical latches do not have mixed inverters as the latch transistors depend on the fabrication process technology. There are two common types of inverters used for SRAM latches: a high load resistor cell employing a high resistor or a depletion load resistor as a pull-up device of the inverter, and a CMOS type cell employing a PMOS transistor as a pull-up device of the inverter. The CMOS type cell can be further sub-divided into a thin-film transistor (TFT) cell employing a thin-film PMOS transistor (TFPT) as the pull-up device, and a full CMOS cell employing a bulk PMOS transistor as the pull-up device. In all cases the pull-down device of the inverter is a bulk NMOS transistor in SRAM construction.
SRAM classified by the total transistor count include 5T (five transistor) SRAM cells, 6T (six transistors) SRAM cells, 2T/2R (two transistor, two resistor) SRAM cells, among many others. Some labels are misnomers as the full transistor count excludes capacitors and resistors needed to make the SRAM cell function correctly. In all cases, each cell includes a bi-stable latch, with two self consisting stable output values: logic 0 (voltage V
S
) and logic 1 (voltage V
D
). The output of the SRAM latch can be set to zero or one through the access transistors. The number of access transistors connected to an SRAM latch defines single port, dual port and multi port memory functionality. Multi-port feature is useful to read and write data in latches at different locations simultaneously.
An SRAM cell in single crystal Silicon (Si) has three different methods of fabrication. The most popular 6T SRAM cell,
FIG. 1
, has six MOSFET transistors. Fabrication is kept simple with no special processing needed by using standard CMOS transistors for the SRAM cell. All six transistors are located in substrate Silicon, and all have high mobility for electron and hole conduction. They are strong devices. The cell area is large, standby current is negligible and the access time is very fast. This configuration is used for high cost, least power, fastest access SRAM memory. In 5T SRAM memory, transistor
111
is not used.
In
FIG. 1A
, the SRAM cell contains a latch comprised of two switching devices (inverters)
104
and
107
back to back and two access transistors
110
and
111
that allow the data terminal
101
and/data (not data) terminal
102
to write and store 0 or 1 in the latch. The two stable operating points of the latch are alterable through the two access transistors
110
,
111
via a common gate terminal
103
. A single inverter
104
cannot hold data indefinitely as an isolated gate node would lose charge from junction leakages. A feedback inverter provides a current drive to the first inverter gate node to replenish lost charge. Each inverter charges the other. The use of CMOS inverters allow both logic “0” state and logic “1” state at the input of the inverter
104
and its opposite state at the input of the inverter
107
indefinitely while power is on. Internally, the inverters
104
,
107
use NMOS transistors
106
,
109
and PMOS transistors
105
,
108
as shown in the latch in FIG.
1
B. Latch transistor dimensions are scaled to ensure proper writing of these two states into the latch, cell stability against alpha particles and noise.
For a number of reasons, among them controllability and consistent current drive being the foremost, the high speed, low power SRAM memory latch is conventionally fabricated on single crystal Silicon using standard CMOS transistors for the SRAM cell. The resulting transistor consumes a relatively large amount of Silicon area.
FIGS. 2A and 2B
show top view and cross sectional view of a conventional CMOS inverter fabricated using a logic twin well process. An NMOS transistor
205
is inside a P-well
208
, while a PMOS transistor
206
is inside an N-well
207
shown in dotted line. PMOS source
211
and drain
212
diffusions are P+ diffusion regions, while NMOS source
214
and drain
213
diffusions are N+ diffusion regions. Due to potential latch-up conditions, a separation distance Y in
FIG. 2
is maintained between the two transistors
205
and
206
. Both Nwell
207
and Pwell
208
are constructed on a substrate
200
of the device, which could be P-type or N-type. Latch-up arises from the P+/N-well/P-Well regions
212
/
207
/
208
and N+/P-Well/N-well regions
213
/
208
/
207
bipolar parasitic transistors near the well boundary as shown in FIG.
2
B. Due to this separation, the Silicon conducting path for current flow can not be constructed in a single active semiconductor geometry. In
FIG. 2B
, PMOS source
211
and body
207
are tied to V
D
203
, and NMOS source
214
and body
208
are tied to V
S
204
. In other applications, the body may be separately biased. The Pwell
208
has to be biased to the lowest potential, while the Nwell
207
has to be biased to the highest potential.
In addition to the single crystal Silicon approach, an SRAM latch can be fabricated as a Resistor-load latch and a TFT PMOS-load latch, both of which have the pull-up device vertically integrated, requiring special poly-crystalline (poly) Silicon for the load device. The resistor-load latch,
FIG. 3A
, has poly Silicon resistors
305
&
308
as pull up devices, instead of PMOS devices. The vertically integrated single poly Silicon film allows elimination of N-wells in the substrate, and a smaller cell area construction. Only four NMOS transistors
110
,
111
in
FIG. 1 and 306
,
309
in
FIG. 3A
are built on substrate Silicon, a reduction from six in full CMOS. These cells consume standby power as one inverter is always conducting, and the power consumption is determined by the resistor value. For 1 Meg density of latches and 1 mA standby current, a resistor value of 1 GOhms is needed. High value intrinsic poly-Silicon resistors are hard to build, and TFT PMOS devices offer better manufacturability. As shown in
FIG. 3B
, TFT PMOS can be also used as active weak PMOS pull-up devices similar to regular PMOS in
FIG. 1
to eliminate stand-by current. As the pull-up device
305
or
315
current drive is very weak, these inverters cannot drive a strong logic one. These configurations of inverters are only used to build latches to construct low cost, high density, higher power, and slower access time SRAM memory. Such memories need complex dual ended sense amplifiers to read the latch data, and are sensitive to noise. As a result, embedded memory and multi-port memory is mostly constructed with CMOS latches.
In all cases the four NMOS transistors
110
,
111
and the two more in inverters
104
and
107
in
FIG. 1A
(
106
,
109
in
FIG. 1B
or
306
,
309
in
FIG. 3A
or
316
,
319
in
FIG. 3B
) are strong. Metal Oxide Semiconductor Field Effect Transistors (MOSFET) fabricated on single crystal Silicon. This is due to the popularity of MOSFET devices over JFET, a

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