Semiconductor integrated memory circuit and trimming method...

Details Semiconductor integrated memory circuit and trimming method... Semiconductor integrated memory circuit and trimming method...

2009-08-12

2011-12-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189050, C365S205000

Reexamination Certificate

active

08077499

ABSTRACT:
A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.

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Office Action issued Nov. 2, 2010, in Japanese Patent Application No. 2008-216198, (with English translaton).
Office Action (with English translation) issued on Aug. 2, 2011, in counterpart Japanese Application No. 2008-216198 (6 pages).

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