Semiconductor integrated logic circuit with sequential...

Details Semiconductor integrated logic circuit with sequential... Semiconductor integrated logic circuit with sequential...

1999-06-11

2001-06-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S083000, C326S113000

Reexamination Certificate

active

06246265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated logic circuit with sequential circuits which has an information holding function in a sleep mode.
2. Description of the Related Art
Conventionally, in a semiconductor integrated logic circuit, a system having a transistor circuit structure is adopted to satisfy a high speed operation in an active mode and low power consumption in a sleep mode. Especially, the semiconductor integrated logic circuit has an information holding function such that a memory data of the sequential circuit is not destroyed at the time of the sleep mode.
For example, the following technique is disclosed in the Japanese Patent No. 2,631,335 (Japanese Laid Open Patent Application (JP-A-Heisei 06-029834). That is, in a semiconductor integrated logic circuit can operate at high speed, the power is supplied through a higher threshold type transistor to block off a leakage current at the time of the sleep mode. Also, a bistable circuit composed of higher threshold type transistors is added to the sequential circuit and the power is directly supplied to the higher threshold type transistors. Thus, the blocking-off of a leakage current and the avoidance from destruction of the memory data at the time of the sleep mode is attained.
FIG. 1
is a circuit diagram which shows a conventional example of the semiconductor integrated logic circuit with sequential circuits, which has an information holding function at the time of the sleep mode.
As shown in
FIG. 1
, a control transistor HP
1
I which is composed of a p-channel type MOSFET with a high threshold value. The control transistor HP
1
I is connected with a higher potential side actual power supply line VDD at the source electrode and a higher potential side quasi power supply line VDDV at the drain electrode. Thus, the electric connection between the higher potential side actual power supply line and the higher potential side quasi power supply line is set to the conductive state or the blocking-off state in response to a sleep mode switching signal SL which is applied to the gate electrode. Also, a control transistor HN
1
I which is composed of an n-channel type MOSFET with a high threshold value. The control transistor HN
1
I is connected with a lower potential side actual power supply voltage GND at the source electrode and a lower potential side quasi power supply voltage GNDV at the drain electrode. Thus, the electric connection between the lower potential side actual power supply line and the lower potential side quasi power supply line is set to the conductive state or the blocking-off state in response to an inverted sleep mode switching signal SLB which is applied to the gate electrode. In this case, the inverted sleep mode switching signal SLB is the signal which is obtained by inverting the sleep mode switching signal SL, and is sent out from a sleep mode control circuit which is not illustrated.
A CMOS circuit group which is composed of the inverter circuits INV
1
I and INV
2
I which are composed of lower threshold type transistors. The inverter circuits INV
1
I and INV
2
I performs the buffering operation of data signals D
1
B and D
2
B which are supplied to the latch circuits
10
A and
10
B, respectively. The inverter circuit INV
1
I is composed of an n-channel type MOSFET as a lower threshold value transistor and a p-channel type MOSFET as a lower threshold value transistor. The gate electrodes of the respective transistors are connected in common and the data signal D
1
B is supplied thereto. The drain electrodes of the respective transistors are connected in common and function as an input terminal of the latch circuit
10
A. The inverter circuit INV
2
I is composed of an n-channel type MOSFET as a lower threshold type transistor and a p-channel type MOSFET as a lower threshold type transistor. The gate electrodes of the respective transistors are connected in common and data signal D
2
B is supplied thereto. The drain electrodes of the respective transistors are connected in common and function as an input terminal to the latch circuit
10
B.
Also, the source electrode of the p-channel type MOSFET with the lower threshold value in the inverter circuit INV
1
I is connected with the higher potential side quasi power supply line VDDV which supplies a higher potential side the quasi power supply voltage through the drain electrode of the control transistor HP
1
I. Also, the source electrode of the n-channel type MOSFET with the lower threshold value in the inverter circuit INV
1
I is connected with the lower potential side quasi power supply line GNDV which supplies a lower potential side quasi power supply voltage through the drain electrode of the control transistor HN
1
I.
Moreover, the structures of the latch circuits
10
A and
10
B of the sequential circuits have the information holding function at the time of the sleep mode in FIG.
1
. The latch circuits
10
A and
10
B will be described.
The latch circuit
10
A is composed of the transfer gates TM
1
A and TM
2
A and three inverter circuits INV
1
A, INV
2
A and INV
3
A. The transfer gate TM
1
A is composed of a n-channel type MOSFET as a lower threshold type transistor and a p-channel type MOSFET as a lower threshold type transistor. The source electrode of one of the transistors and the drain electrode of the other of the transistors are connected in parallel in an alternate manner. One of the electrodes of the transfer gate TM
1
A is connected with an output terminal of the inverter circuit INV
1
I and the other electrode thereof is connected with the input terminal of the inverter circuit INV
1
A.
Moreover, a clock signal &phgr; is applied to the gate electrode of the n-channel type MOSFET as the lower threshold type transistor in the transfer gate TM
1
A. An inverted clock signal *&phgr; which is the inverted signal of the clock signal &phgr; is applied to the gate electrode of the p-channel type MOSFET as the lower threshold type transistor.
The transfer gate TM
2
A and the transfer gate TM
1
A have the same structure and are bidirectional. One of the electrodes of the transfer gate TM
2
A is connected with the input terminal of the inverter circuit INV
1
A and the other electrode thereof is connected with the ago output of the inverter circuit INV
2
A. It should be noted that the transistors of the transfer gate TM
2
A may be lower threshold type MOSFETs or high threshold type MOSFETs.
The inverter circuits INV
1
A, INV
2
A and INV
3
A have the same structure as those of the inverter circuits INV
1
I and INV
2
I, and each of transistors of the inverter circuit INV
1
A is an MOSFET with the lower threshold value. Each of the transistors of the inverter circuits INV
2
A and INV
3
A is an MOSFET with the high threshold value.
Also, the control transistor HP
1
A which is composed of a p-channel type MOSFET with the high threshold value sets the electric connection with the drain electrode to the conductive state or the blocking-off state in response to the mode switching signal SL. Also, the control transistor HN
1
A which is composed of an n-channel type MOSFET with the high threshold value, is connected with the lower potential side actual power supply voltage GND at the source electrode. The control transistor HN
1
A sets the electric connection with the drain electrode to the conductive state or the blocking-off state in response to the inverted sleep mode switching signal SLB applied to the gate electrode thereof.
Also, the source electrode of the p-channel type MOSFET with the lower threshold value in the inverter circuit INV
1
A is connected with the drain electrode of the control transistor HP
1
A. The source electrode of the n-channel type MOSFET with the lower threshold value in the inverter circuit INV
1
A is connected with the drain electrode of the control transistor HN
1
A. Also, the inverter circuit INV
3
A is connected with the inverter circuit INV
1
A in parallel. The inverter circuit INV
3
A is different from the inverter circuit INV
1
A in that the inver

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