Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-05-10
2004-07-13
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S090000, C326S101000
Reexamination Certificate
active
06762619
ABSTRACT:
Japanese Patent Application No. 2001-143632 filed on May 14, 2001, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a semiconductor integrated device and electronic equipment including the same.
BACKGROUND
In recent years, the Universal Serial Bus (USB) has attracted attention as an interface standard for connecting a personal computer with a peripheral device (electronic equipment in a broad sense). The USB has the advantage of enabling peripheral devices such as a mouse, keyboard, and printer, which are conventionally connected through connectors according to different standards, to be connected through the same standard connectors. Moreover, so-called plug & play and hot plug can be realized by the USB.
However, the USB has a problem in which the transfer rate is lower than that of the IEEE 1394, which has also attracted attention as a serial bus interface standard.
To deal with this problem, the USB 2.0 standard enabling a data transfer rate of 480 Mbps (HS mode), which is remarkably higher than that of the USB 1.1, while maintaining backward compatibility with the USB 1.1 standard has been developed and has attracted attention. The UTMI (USB 2.0 Transceiver Macrocell Interface) which defines the interface specification of the physical layer circuits and part of the logical layer circuits of the USB 2.0 has been also developed.
SUMMARY
One aspect of the present invention relates to a semiconductor integrated device which drives current through first and second signal lines forming a differential pair, the semiconductor integrated device comprising:
first and second pads through which current is driven exclusively in a signal-output period, the first and second pads being connected to the first and second signal lines, respectively; and
a third pad through which current is driven in a period other than the signal-output period,
wherein the third pad is disposed between the first and second pads.
REFERENCES:
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6674302 (2004-01-01), Yen
Kasahara Shoichiro
Nakada Akira
Oliff & Berridge, plc
Seiko Epson Corporation
Tran Anh Q.
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